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| author | Myles Watson <mylesgw@gmail.com> | 2009-10-16 16:32:57 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-10-16 16:32:57 +0000 |
| commit | 0f61a4fc98f135c0ed22c67ee3241bf5670a61e2 (patch) | |
| tree | b3867408477cdf8a3a2374f32d91b4f3936b7486 /src/mainboard/amd/serengeti_cheetah_fam10/Options.lb | |
| parent | 9969bdc4fb3d36a39ed9efb67ef0bf638a4e8e09 (diff) | |
Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah_fam10/Options.lb')
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/Options.lb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb index a5ba422069..2d82dfde4e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -98,7 +98,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_PCI_BUS_SEGN_BITS @@ -135,7 +135,7 @@ default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. -default CONFIG_LB_MEM_TOPK=16384 +default CONFIG_RAMTOP=16384*1024 ## ## Build code for the fallback boot |