CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in

serengeti_cheeatah


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

14 files changed, 360 insertions, 122 deletions

diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb
index f395e4138d..fdff457c0d 100644
--- a/src/mainboard/amd/serengeti_cheetah/Config.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Config.lb
@@ -105,6 +105,20 @@ if HAVE_ACPI_TABLES
                         action  "mv pci2.hex ssdt2.c"
             end
             object ./ssdt2.o
+            makerule ssdt3.c
+                        depends "$(MAINBOARD)/dx/pci3.asl"
+                        action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl"
+                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
+                        action  "mv pci3.hex ssdt3.c"
+            end
+            object ./ssdt3.o
+            makerule ssdt4.c
+                        depends "$(MAINBOARD)/dx/pci4.asl"
+                        action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl"
+                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
+                        action  "mv pci4.hex ssdt4.c"
+            end
+            object ./ssdt4.o
         end
 end
 
diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb
index 91712ece99..b4d69ca9da 100644
--- a/src/mainboard/amd/serengeti_cheetah/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Options.lb
@@ -89,6 +89,8 @@ uses MEM_TRAIN_SEQ
 
 uses WAIT_BEFORE_CPUS_INIT
 
+uses CONFIG_USE_PRINTK_IN_CAR
+
 ###
 ### Build options
 ###
@@ -212,9 +214,12 @@ default DCACHE_RAM_SIZE=0x08000
 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
+
+##
+## for rev F training on AP purpose
+##
 default CONFIG_AP_CODE_IN_CAR=1
 default MEM_TRAIN_SEQ=1
-
 default WAIT_BEFORE_CPUS_INIT=1
 
 ##
@@ -271,8 +276,8 @@ default CONFIG_ROM_STREAM = 1
 ##
 ## The default compiler
 ##
-default CC="$(CROSS_COMPILE)gcc-3.4.5 -m32"
-default HOSTCC="gcc-3.4.5"
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
@@ -282,6 +287,7 @@ default CONFIG_GDB_STUB=0
 ##
 ## The Serial Console
 ##
+default CONFIG_USE_PRINTK_IN_CAR=0
 
 # To Enable the Serial Console
 default CONFIG_CONSOLE_SERIAL8250=1
diff --git a/src/mainboard/amd/serengeti_cheetah/a b/src/mainboard/amd/serengeti_cheetah/a
deleted file mode 100644
index d6a8f398e0..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/a
+++ /dev/null
@@ -1,25 +0,0 @@
-echo "Creating for ACPI hex for bus 1 Conf"
-cd dx
-iasl -tc dsdt_lb.dsl
-rm DSDT.aml
-mv dsdt_lb.hex ../dsdt.c
-iasl -tc pci2.asl
-rm SSDT2.aml
-perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex
-mv pci2.hex ../ssdt2.c
-cd ..
-echo "Creating for ACPI hex for bus 0 Conf"
-cd dx_bus0
-iasl -tc dsdt_lb.dsl
-rm DSDT.aml
-mv dsdt_lb.hex ../dsdt_bus0.c
-iasl -tc pci2.asl
-rm SSDT2.aml
-perl -e 's/AmlCode/AmlCode_ssdt2/g' -pi pci2.hex
-mv pci2.hex ../ssdt2_bus0.c
-cd ..
-echo "Creating ssdt"
-iasl -tc ssdt_lb_x.dsl
-rm SSDT.aml
-perl -e 's/AmlCode/AmlCode_ssdt/g' -pi ssdt_lb_x.hex
-mv ssdt_lb_x.hex ssdt.c
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
index e4cf72b268..1ba92e2b64 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
@@ -42,12 +42,8 @@ extern unsigned char AmlCode_ssdt[];
 
 #if ACPI_SSDTX_NUM >= 1
 extern unsigned char AmlCode_ssdt2[];
-//extern unsigned char AmlCode_ssdt3[];
-//extern unsigned char AmlCode_ssdt4[];
-//extern unsigned char AmlCode_ssdt5[];
-//extern unsigned char AmlCode_ssdt6[];
-//extern unsigned char AmlCode_ssdt7[];
-//extern unsigned char AmlCode_ssdt8[];
+extern unsigned char AmlCode_ssdt3[];
+extern unsigned char AmlCode_ssdt4[];
 #endif
 
 #define IO_APIC_ADDR	0xfec00000UL
@@ -90,6 +86,51 @@ unsigned long acpi_fill_madt(unsigned long current)
                                 gsi_base+=7;
                         }
                 }
+
+                int i;
+                int j = 0;
+
+                for(i=1; i< sysconf.hc_possible_num; i++) {
+			unsigned d;
+                        if(!(sysconf.pci1234[i] & 0x1) ) continue;
+                        // 8131 need to use +4
+			
+                        switch (sysconf.hcid[i]) {
+                        case 1:
+				d = 7;
+				break;
+			case 3:
+				d = 4;
+				break;
+			}
+                        switch (sysconf.hcid[i]) {
+                        case 1:
+			case 3:
+                                dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+                                if (dev) {
+                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                                        if (res) {
+                                                current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
+                                                        res->base, gsi_base );
+                                                gsi_base+=d;
+                                        }
+                                }
+                                dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+                                if (dev) {
+                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                                        if (res) {
+                                                current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
+                                                        res->base, gsi_base );
+                                                gsi_base+=d;
+
+                                        }
+                                }
+                                break;
+                        }
+
+                        j++;
+                }
+
         }
 
 	current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
@@ -112,6 +153,29 @@ extern void get_bus_conf(void);
 
 extern void update_ssdt(void *ssdt);
 
+void update_ssdtx(void *ssdtx, int i)
+{
+        uint8_t *PCI;
+        uint8_t *HCIN;
+        uint8_t *UID;
+
+        PCI = ssdtx + 0x32;
+        HCIN = ssdtx + 0x39;
+        UID = ssdtx + 0x40;
+
+        if(i<7) {
+                *PCI  = (uint8_t) ('4' + i - 1);
+        }
+        else {
+                *PCI  = (uint8_t) ('A' + i - 1 - 6);
+        }
+        *HCIN = (uint8_t) i;
+        *UID  = (uint8_t) (i+3);
+
+        /* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
@@ -126,6 +190,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
 	acpi_header_t *ssdtx;
+	unsigned char *p;
 
 	unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
 
@@ -195,27 +260,42 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_add_table(rsdt,ssdt);
 
 #if ACPI_SSDTX_NUM >= 1
-	// we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1] 
-	AmlCode_ssdtx[1] = AmlCode_ssdt2;
-//	AmlCode_ssdtx[2] = AmlCode_ssdt3;
-//	AmlCode_ssdtx[3] = AmlCode_ssdt4;
-//      AmlCode_ssdtx[4] = AmlCode_ssdt5;
-//      AmlCode_ssdtx[5] = AmlCode_ssdt6;
-//      AmlCode_ssdtx[6] = AmlCode_ssdt7;
-//      AmlCode_ssdtx[7] = AmlCode_ssdt8;
-
-	//same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table
-	
-	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
-		if((sysconf.pci1234[i] & 1) != 1 ) continue;
-	        printk_debug("ACPI:    * SSDT for PCI%d\n", i+1); //pci0 and pci1 are in dsdt
-        	ssdtx = (acpi_header_t *)current;
-	        current += ((acpi_header_t *)AmlCode_ssdtx[i])->length;
-	        memcpy((void *)ssdtx, (void *)AmlCode_ssdtx[i], ((acpi_header_t *)AmlCode_ssdtx[i])->length);
-        	acpi_add_table(rsdt,ssdtx);
-	}
-#endif
 
+        //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
+
+        for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+                if((sysconf.pci1234[i] & 1) != 1 ) continue;
+                uint8_t c;
+                if(i<7) {
+                        c  = (uint8_t) ('4' + i - 1);
+                }
+                else {
+                        c  = (uint8_t) ('A' + i - 1 - 6);
+                }
+                printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
+                current   = ( current + 0x07) & -0x08;
+                ssdtx = (acpi_header_t *)current;
+                switch(sysconf.hcid[i]) {
+                case 1: //8132
+                        p = AmlCode_ssdt2;
+                        break;
+                case 2: //8151
+                        p = AmlCode_ssdt3;
+                        break;
+		case 3: //8131
+                        p = AmlCode_ssdt4;
+                        break;
+                default:
+                        continue;
+                }
+                current += ((acpi_header_t *)p)->length;
+                memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *)p)->length);
+                update_ssdtx((void *)ssdtx, i);
+                ssdtx->checksum = 0;
+                ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length);
+                acpi_add_table(rsdt,ssdtx);
+        }
+#endif
 
 	/* FACS */
 	printk_debug("ACPI:    * FACS\n");
diff --git a/src/mainboard/amd/serengeti_cheetah/apc_auto.c b/src/mainboard/amd/serengeti_cheetah/apc_auto.c
index d6a19e6e96..8f707884f2 100644
--- a/src/mainboard/amd/serengeti_cheetah/apc_auto.c
+++ b/src/mainboard/amd/serengeti_cheetah/apc_auto.c
@@ -21,6 +21,16 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
+
+#if CONFIG_USE_INIT == 0
+	#include "lib/memcpy.c"
+ #if CONFIG_USE_PRINTK_IN_CAR == 1
+	#include "lib/uart8250.c"
+	#include "console/vtxprintf.c"
+	#include "arch/i386/lib/printk_init.c"
+ #endif
+#endif
+
 #include "arch/i386/lib/console.c"
 
 #if 0 
@@ -40,10 +50,6 @@ static void post_code(uint8_t value) {
 
 #include "lib/delay.c"
 
-#if CONFIG_USE_INIT == 0
-	#include "lib/memcpy.c"
-#endif
-
 
 //#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
@@ -72,7 +78,11 @@ void hardwaremain(int ret_addr)
 
 	id = get_node_core_id_x();
 
+#if CONFIG_USE_PRINTK_IN_CAR
+        printk_debug("CODE IN CACHE ON NODE: %02x\n");
+#else
         print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+#endif
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
diff --git a/src/mainboard/amd/serengeti_cheetah/c b/src/mainboard/amd/serengeti_cheetah/c
deleted file mode 100644
index 0abeb0ea86..0000000000
--- a/src/mainboard/amd/serengeti_cheetah/c
+++ /dev/null
@@ -1,5 +0,0 @@
-rm dsdt.c
-rm ssdt2.c
-rm dsdt_bus0.c
-rm ssdt2_bus0.c
-rm ssdt.c
diff --git a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
index c338704553..4eb7a71070 100644
--- a/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
+++ b/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
@@ -15,16 +15,13 @@
 
 
 //used by init_cpus and fidvid
-#define K8_SET_FIDVID 1
+#define K8_SET_FIDVID 0
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-//0: three for in bsp, only this one support F0_F1 workaround
-//1: on every core0
-//2: one for on bsp
-//#define MEM_TRAIN_SEQ 1
-
+#if K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
 
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -59,14 +56,19 @@ static void post_code(uint8_t value) {
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "cpu/x86/bist.h"
 
 #if USE_FAILOVER_IMAGE==0
+#include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
 
 #if CONFIG_USE_INIT == 0
 	#include "lib/memcpy.c"
+ #if CONFIG_USE_PRINTK_IN_CAR == 1
+	#include "lib/uart8250.c"
+	#include "console/vtxprintf.c"
+	#include "arch/i386/lib/printk_init.c"
+ #endif
 #endif
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -123,12 +125,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
         return smbus_read_byte(device, address);
 }
 
-#include "northbridge/amd/amdk8/amdk8_f.h"
+#include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 
-#include "northbridge/amd/amdk8/raminit_f.c"
+#include "northbridge/amd/amdk8/raminit.c"
 
 #include "sdram/generic_sdram.c"
 
@@ -263,8 +265,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
         unsigned bsp_apicid = 0;
 
         if (bist == 0) {
-	        //It's the time to set ctrl in sysinfo now;
-	        fill_mem_ctrl(CONFIG_MAX_PHYSICAL_CPUS, sysinfo->ctrl, spd_addr);
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
@@ -281,7 +281,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 
-        setup_serengeti_cheetah_resource_map();
+        setup_mb_resource_map();
 #if 0
         dump_pci_device(PCI_DEV(0, 0x18, 0));
 	dump_pci_device(PCI_DEV(0, 0x19, 0));
@@ -350,10 +350,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 	allow_all_aps_stop(bsp_apicid);
 
-#if 0
         //It's the time to set ctrl in sysinfo now;
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-#endif
 
 	enable_smbus();
 
diff --git a/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl b/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl
index a62ba98333..217491ad0a 100644
--- a/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl
+++ b/src/mainboard/amd/serengeti_cheetah/dx/pci2.asl
@@ -23,21 +23,21 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
 	External (\_SB.PCI0.LNKC, DeviceObj)
 	External (\_SB.PCI0.LNKD, DeviceObj)
 
-        Device (PCI2)
+        Device (PCIX)
         {
 
 	    // BUS ? Second HT Chain
-	    Name (HCIN, 0x01)  // HC2
+	    Name (HCIN, 0xcc)  // HC2 0x01
+            
+	    Name (_UID,  0xdd)  // HC 0x03
 
 	    Name (_HID, "PNP0A03") 
 
             Method (_ADR, 0, NotSerialized) //Fake bus should be 0
 	    {
-		Return (DADD(GHCN(HCIN), 0x00180000))
+		Return (DADD(GHCN(HCIN), 0x00000000))
 	    }
 	
-            Name (_UID,  0x03) 
-
             Method (_BBN, 0, NotSerialized)
             {
                 Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
diff --git a/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl b/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl
index 045d090392..03443adce5 100644
--- a/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl
+++ b/src/mainboard/amd/serengeti_cheetah/dx/pci2_hc.asl
@@ -1 +1 @@
-	Include ("amd8151.asl")
+	Include ("amd8132_2.asl")
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
index cc4c0e4219..d76b1ef2b9 100644
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
@@ -42,13 +42,44 @@ extern void get_sblk_pci1234(void);
 
 static unsigned get_bus_conf_done = 0;
 
+static unsigned get_hcid(unsigned i)
+{
+        unsigned id = 0;
+
+        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+
+        unsigned devn = sysconf.hcdn[i] & 0xff;
+
+        device_t dev;
+
+        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+
+        switch (dev->device) {
+        case 0x7458: //8132
+                id = 1;
+                break;
+        case 0x7454: //8151
+                id = 2;
+		break;
+        case 0x7450: //8131
+                id = 3;
+                break;
+        }
+
+        // we may need more way to find out hcid: subsystem id? GPIO read ?
+
+        // we need use id for 1. bus num, 2. mptable, 3. acpi table
+
+        return id;
+}
+
 void get_bus_conf(void)
 {
 
 	unsigned apicid_base;
 
         device_t dev;
-	int i;
+	int i, j;
 	struct mb_sysconf_t *m;
 
 	if(get_bus_conf_done == 1) return; //do it only once
@@ -69,7 +100,6 @@ void get_bus_conf(void)
 	
 	sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
 	m->sbdn3 = sysconf.hcdn[0] & 0xff;
-	m->sbdn5 = sysconf.hcdn[1] & 0xff;
 
 	m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
 	m->bus_8111_0 = m->bus_8132_0;
@@ -112,22 +142,69 @@ void get_bus_conf(void)
         }
 
         /* HT chain 1 */
-	if((sysconf.pci1234[1] & 0x1) == 1) {
-		m->bus_8151_0 = (sysconf.pci1234[1] >> 16) & 0xff;
-                /* 8151 */
-		dev = dev_find_slot(m->bus_8151_0, PCI_DEVFN(m->sbdn5+1, 0));
-
-              	if (dev) {
-                       	m->bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-//                        printk_debug("bus_8151_1=%d\n",bus_8151_1);
-       	                m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-              	        m->bus_isa++;
-              	}
-       		else {
-                	printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151_0, m->sbdn5+1);
-        	}
+        j=0;
+        for(i=1; i< sysconf.hc_possible_num; i++) {
+                if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+                // check hcid type here
+                sysconf.hcid[i] = get_hcid(i);
+
+                switch(sysconf.hcid[i]) {
+
+                case 1: //8132
+		case 3: //8131
+
+                        m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
+
+                        m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
+
+                        /* 8132-1 */
+                        dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0));
+                        if (dev) {
+                                m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        }
+                        else {
+                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
+                        }
+
+                        /* 8132-2 */
+                        dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0));
+                        if (dev) {
+                                m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                                m->bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                                m->bus_isa++;
+                //              printk_debug("bus_isa=%d\n",bus_isa);
+                                }
+                        else {
+                                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
+                        }
+
+                        break;
+
+                case 2: //8151
+
+                        m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
+                        m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
+                        /* 8151 */
+                        dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0));
+
+                        if (dev) {
+                                m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+        //                        printk_debug("bus_8151_1=%d\n",bus_8151[j][1]);
+                                m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                                m->bus_isa++;
+                        }
+                        else {
+                                printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
+                        }
+
+                        break;
+                }
+
+                j++;
         }
 
+
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(3);
@@ -137,4 +214,9 @@ void get_bus_conf(void)
 	m->apicid_8111 = apicid_base+0;
 	m->apicid_8132_1 = apicid_base+1;
 	m->apicid_8132_2 = apicid_base+2;
+        for(i=0;i<j;i++) {
+                m->apicid_8132a[i][0] = apicid_base + 3 + i*2;
+                m->apicid_8132a[i][1] = apicid_base + 3 + i*2 + 1;
+        }
+
 }
diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
index fb793078df..d6837c061b 100644
--- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
@@ -113,14 +113,20 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 //pcix bridge
 //        write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 //        pirq_info++; slot_num++;
-	
-	if(sysconf.pci1234[1] & 0xf) {
-	//agp bridge
-        	write_pirq_info(pirq_info, m->bus_8151_0, (m->sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); 
-	}	
 
-        pirq_info++; slot_num++;
-             
+	int j = 0;
+
+        for(i=1; i< sysconf.hc_possible_num; i++) {
+                if(!(sysconf.pci1234[i] & 0x1) ) continue;
+                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+                unsigned devn = sysconf.hcdn[i] & 0xff;
+
+                write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+                pirq_info++; slot_num++;
+                j++;
+
+        }
+	
 	pirq->size = 32 + 16 * slot_num; 
 
         for (i = 0; i < pirq->size; i++)
diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h
index 7368f05b4e..189c518414 100644
--- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h
+++ b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h
@@ -9,14 +9,20 @@ struct mb_sysconf_t {
 	unsigned char bus_8132_2;
 	unsigned char bus_8111_0;
 	unsigned char bus_8111_1;
-	unsigned char bus_8151_0;
-	unsigned char bus_8151_1;
-	unsigned apicid_8111;
-	unsigned apicid_8132_1;
-	unsigned apicid_8132_2;
-
-	unsigned sbdn3;
-	unsigned sbdn5;
+
+        unsigned char bus_8132a[7][3];
+
+        unsigned char bus_8151[7][2];
+
+        unsigned apicid_8111;
+        unsigned apicid_8132_1;
+        unsigned apicid_8132_2;
+        unsigned apicid_8132a[7][2];
+
+        unsigned sbdn3;
+        unsigned sbdn3a[7];
+        unsigned sbdn5[7];
+
 };
 
 #endif
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index d27c786631..9b8cbec2cd 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -20,7 +20,7 @@ void *smp_write_config_table(void *v)
         struct mp_config_table *mc;
 
         unsigned char bus_num;
-	int i;
+	int i, j;
 	struct mb_sysconf_t *m;
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -72,6 +72,34 @@ void *smp_write_config_table(void *v)
 				smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
 			}
                 }
+
+                j = 0;
+
+                for(i=1; i< sysconf.hc_possible_num; i++) {
+                        if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+                        switch(sysconf.hcid[i]) {
+                        case 1: // 8132
+			case 3: // 8131
+                                dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+                                if (dev) {
+                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                                        if (res) {
+                                                smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+                                        }
+                                }
+                                dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+                                if (dev) {
+                                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                                        if (res) {
+                                                smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+                                        }
+                                }
+                                break;
+                        }
+                        j++;
+                }
+
 	}
   
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */	
@@ -95,11 +123,6 @@ void *smp_write_config_table(void *v)
 // Onboard AMD USB
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
 
-	if(sysconf.pci1234[1] & 0xf) {
-	//  Slot AGP
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151_1, 0x0, m->apicid_8111, 0x11);
-	}	
-
 //Slot 3  PCI 32
         for(i=0;i<4;i++) {
                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
@@ -123,6 +146,50 @@ void *smp_write_config_table(void *v)
                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
         }
 
+        j = 0;
+
+        for(i=1; i< sysconf.hc_possible_num; i++) {
+                if(!(sysconf.pci1234[i] & 0x1) ) continue;
+                int ii;
+                device_t dev;
+                struct resource *res;
+                switch(sysconf.hcid[i]) {
+                case 1:
+		case 3:
+                        dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+                        if (dev) {
+                                res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                                if (res) {
+                                        //Slot 1 PCI-X 133/100/66
+                                        for(ii=0;ii<4;ii++) {
+                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+                                        }
+                                }
+                        }
+
+                        dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+                        if (dev) {
+                                res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                                if (res) {
+                                        //Slot 2 PCI-X 133/100/66
+                                        for(ii=0;ii<4;ii++) {
+                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+                                        }
+                                }
+                        }
+
+                        break;
+                case 2:
+
+                //  Slot AGP
+                        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
+                        break;
+                }
+
+                j++;
+        }
+
+
 
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c
index e42bbcc1af..e5fc91b30e 100644
--- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c
+++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c
@@ -1,9 +1,8 @@
 /*
- * AMD serengeti_cheetah needs a different resource map
  *
  */
 
-static void setup_serengeti_cheetah_resource_map(void)
+static void setup_mb_resource_map(void)
 {
 	static const unsigned int register_values[] = {
 		/* Careful set limit registers before base registers which contain the enables */