remove trailing whitespace

Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

9 files changed, 62 insertions, 62 deletions

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 3fb0e875db..3cfd741755 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -91,7 +91,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       return CalloutStatus;
     }
   }
- 
+
   return CalloutStatus;
 }
 
@@ -289,7 +289,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
     } else {
       /* Otherwise, add freed node to the start of the list
-         Update NextNodeOffset and BufferSize to include the 
+         Update NextNodeOffset and BufferSize to include the
          size of BIOS_BUFFER_NODE
       */
       AllocNodePtr->NextNodeOffset = FreedNodeOffset;
@@ -470,7 +470,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-   
+
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
@@ -563,13 +563,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ; 
+        Data8 &= ~(UINT8)BIT6 ;
         Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
         Status = AGESA_SUCCESS;
         break;
@@ -586,7 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
         break;
       case DeassertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ; 
+        Data8 |= BIT6 ;
         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
         Status = AGESA_SUCCESS;
         break;
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h
index b187fa25c0..b7c78830b4 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.h
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.h
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #ifndef _BIOS_CALLOUT_H_
 #define _BIOS_CALLOUT_H_
 
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
index 59d31efb77..b0389b82d9 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
@@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }       
+        }
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
@@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   //
   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
   //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
                                          sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
@@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE); 
+    ASSERT(FALSE);
     return;
   }
-  
+
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
@@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 
   AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
   BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
- 
+
   LibAmdMemFill (BrazosPcieComplexListPtr,
                    0,
                    sizeof (PCIe_COMPLEX_DESCRIPTOR),
@@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
                    0,
                    sizeof (PCIe_PORT_DESCRIPTOR) * 5,
                    &InitEarly->StdHeader);
-     
+
   LibAmdMemFill (BrazosPcieDdiPtr,
                    0,
                    sizeof (PCIe_DDI_DESCRIPTOR) * 2,
@@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
   ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
-  InitEarly->GnbConfig.PsppPolicy      = 0; 
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;
 }
 
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
index f35d8db723..b51089f7f6 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
@@ -25,42 +25,42 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
                                            //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
@@ -68,5 +68,5 @@ VOID
 OemCustomizeInitEarly (
   IN  OUT AMD_EARLY_PARAMS    *InitEarly
   );
-  
+
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index 74aa73d49f..9d9f864141 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -86,11 +86,11 @@ agesawrapper_amdinitcpuio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
-  
+
   /* Enable legacy video routing: D18F1xF4 VGA Enable */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
   PciData = 1;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
   /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
    * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
@@ -99,21 +99,21 @@ agesawrapper_amdinitcpuio (
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
   PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
   PciData |= 1 << 7;    // set NP (non-posted) bit
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
   PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
   /* Map the remaining PCI hole as posted MMIO */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
   PciData = 0x00FECF00; // last address before non-posted range
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
   MsrReg = (MsrReg >> 8) | 3;
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
   PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
   /* Send all IO (0000-FFFF) to southbridge. */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
   PciData = 0x0000F000;
@@ -135,7 +135,7 @@ agesawrapper_amdinitmmio (
   UINT32                        PciData;
   PCI_ADDR                      PciAddress;
   AMD_CONFIG_PARAMS             StdHeader;
-  
+
   UINT8                         BusRangeVal = 0;
   UINT8                         BusNum;
   UINT8                         Index;
@@ -166,10 +166,10 @@ agesawrapper_amdinitmmio (
   /* Set Ontario Link Data */
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
   PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
   PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
   PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
   Status = AGESA_SUCCESS;
   return (UINT32)Status;
@@ -313,7 +313,7 @@ agesawrapper_amdinitenv (
   /* Initialize Subordinate Bus Number and Secondary Bus Number
    * In platform BIOS this address is allocated by PCI enumeration code
      Modify D1F0x18
-   */  
+   */
   PciAddress.Address.Bus = 0;
   PciAddress.Address.Device = 1;
   PciAddress.Address.Function = 0;
@@ -480,10 +480,10 @@ agesawrapper_amdinitlate (
   return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Func, 
-  UINT32 Data, 
+  UINT32 Func,
+  UINT32 Data,
   VOID *ConfigPtr
   )
 {
diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c
index 9da0e0e3a8..2bd27d6f42 100644
--- a/src/mainboard/amd/persimmon/dimmSpd.c
+++ b/src/mainboard/amd/persimmon/dimmSpd.c
@@ -16,7 +16,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
- 
+
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
@@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    UINT64 limit;
 
    address |= 1; // set read bit
-   
+
    __outbyte (iobase + 0, 0xFF);                // clear error status
    __outbyte (iobase + 1, 0x1F);                // clear error status
    __outbyte (iobase + 3, offset);              // offset in eeprom
@@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  *
  * readspd - Read one or more SPD bytes from a DIMM.
  *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid 
+ *           Optimization relies on autoincrement to avoid
  *           sending offset for every byte.
  *          Reads 128 bytes in 7-8 ms at 400 KHz.
  */
@@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
-   
+
    return 0;
    }
 
@@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
    {
    int spdAddress, ioBase;
 
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
    if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-   
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
    if (spdAddress == 0) return AGESA_ERROR;
    ioBase = 0xB00;
    setupFch (ioBase);
diff --git a/src/mainboard/amd/persimmon/dimmSpd.h b/src/mainboard/amd/persimmon/dimmSpd.h
index 069c34a6fc..069c34a6fc 100755..100644
--- a/src/mainboard/amd/persimmon/dimmSpd.h
+++ b/src/mainboard/amd/persimmon/dimmSpd.h
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 4bc5b48218..2d28023574 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -69,22 +69,22 @@ void get_bus_conf(void)
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
  * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are 
- * written into RAM.  The routine that is responsible for writing the tables is 
- * "write_tables", called near the end of "hardwaremain".  There is no platform 
- * specific entry point between the S3 resume decision point and the call to 
- * "write_tables", and the next platform specific entry points are the calls to 
- * the ACPI table write functions.  The first of ose would seem to be the right 
- * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM.  The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions.  The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
  * called before the ACPI tables are written.  This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate(); 
+  status = agesawrapper_amdinitlate();
   if(status) {
     printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
   }
-	
+
   sbdn_sb800 = 0;
 
   for (i = 0; i < 3; i++) {
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index a3b4b5c95e..546d9bd393 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -61,10 +61,10 @@ static void *smp_write_config_table(void *v)
   mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
-  
+
   u32 dword;
   u8 byte;
-    
+
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
@@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v)
   /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
 
   /* on board NIC & Slot PCIE.  */
-  
+
   /* PCI slots */
   /* PCI_SLOT 0. */
   PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);