diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-07-16 09:33:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-18 11:22:32 +0000 |
| commit | bb5ccbd42fd3e702f71017dd186ae98278ffeeac (patch) | |
| tree | 2612f6e45ad12406c20b3c446451cfd1d44777b3 /src/mainboard/amd/persimmon | |
| parent | 30fce518f65335f66b53189a55638b26a1fdbe3a (diff) | |
mb/amd/*/BiosCallOuts.c: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I37ed13e1fa318ca0f8381f5b1b409bf80fa4da11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/amd/persimmon')
| -rw-r--r-- | src/mainboard/amd/persimmon/BiosCallOuts.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 46a33087dc..fb978b8287 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -6,8 +6,8 @@ #include <northbridge/amd/agesa/BiosCallOuts.h> #include <SB800.h> -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -24,7 +24,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); /* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. @@ -33,7 +33,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP } /* PCIE slot reset control */ -static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; PCIe_SLOT_RESET_INFO *ResetInfo; @@ -49,15 +49,15 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot switch (ResetInfo->ResetControl) { case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG50); Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); + Write64Mem8(GpioMmioAddr + SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); + Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG50); Data8 |= BIT6; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); + Write64Mem8(GpioMmioAddr + SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; } |