diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-06-11 16:36:37 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 21:45:28 +0200 |
| commit | 32ab283b1086ef53fadcd4be92df6e41c5d06438 (patch) | |
| tree | b6abc67d0383413dc091d8d6d9639916ddf53066 /src/mainboard/amd/persimmon | |
| parent | e221aad27fb860f31be089180d920df9d2243ae2 (diff) | |
cpu: Add CPU microcode file to cbfs with 16-byte alignment
On x86 there is a 16-byte alignment requirement for the
addresses containing the CPU microcode. The cbfs files
containing the microcode are used in memory-mapped fashion
when loading new mircocode. Therefore, the data payload's
address/offset of a cbfs file in flash dictates the resulting
alignment. Fix this by processing the CPU microcode cbfs
file separately as it uses $(CBFSTOOL) to find the proper
location within the provided rom image.
Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/persimmon')
0 files changed, 0 insertions, 0 deletions