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authorMike Loptien <mike.loptien@se-eng.com>2013-03-05 14:21:28 -0700
committerMarc Jones <marc.jones@se-eng.com>2013-03-08 23:59:13 +0100
commit4733c647bc64cef86f03efd64a145e4da6fef123 (patch)
tree5c5387017dfe950425366a7240f6d17052cd4a5f /src/mainboard/amd/persimmon
parentae0e8d3613ad9cb6872c58cd95fc9774b3b17f5b (diff)
Persimmon DSDT: Add secondary bus range to PCI0
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. This change will apply to other AMD mainboards and will be in a different commit. Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2592 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/amd/persimmon')
-rw-r--r--src/mainboard/amd/persimmon/dsdt.asl16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl
index 582ab7fa64..148d7b074b 100644
--- a/src/mainboard/amd/persimmon/dsdt.asl
+++ b/src/mainboard/amd/persimmon/dsdt.asl
@@ -1477,6 +1477,22 @@ DefinitionBlock (
} /* end Ac97modem */
Name(CRES, ResourceTemplate() {
+ /* Set the Bus number and Secondary Bus number for the PCI0 device
+ * The Secondary bus range for PCI0 lets the system
+ * know what bus values are allowed on the downstream
+ * side of this PCI bus if there is a PCI-PCI bridge.
+ * PCI busses can have 256 secondary busses which
+ * range from [0-0xFF] but they do not need to be
+ * sequential.
+ */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x00FF, /* range maximum */
+ 0x0000, /* translation */
+ 0x0100, /* length */
+ ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
+
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,