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authorMartin Roth <martin.roth@se-eng.com>2013-02-24 12:58:33 -0700
committerMartin Roth <martin.roth@se-eng.com>2013-03-07 18:29:38 +0100
commit45f72ce60f41a655514c29698678cf3c1fb0c1a9 (patch)
tree104b7fc14f6d638af3e17345bda2532cb958f075 /src/mainboard/amd/persimmon/mainboard.c
parent3b2653b1fc207111e96585a273294cedffc49141 (diff)
AMD Persimmon: Use SPD read code from F14 wrapper
Changes: - Get rid of the persimmon mainboard specific code which has been moved into the wrapper as a platform generic function in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I5f017dbb8dee5a09ec19734a6069ff9b71a6ab50 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2500 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/amd/persimmon/mainboard.c')
-rw-r--r--src/mainboard/amd/persimmon/mainboard.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 99e1c306a2..6cba175370 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -73,6 +73,15 @@ static void mainboard_enable(device_t dev)
*(misc_mem_clk_cntrl + 2) = 0x00;
*(misc_mem_clk_cntrl + 3) = 0x00;
*(misc_mem_clk_cntrl + 4) = 0x00;
+
+ /*
+ * Initialize ASF registers to an arbitrary address because someone
+ * long ago set things up this way inside the SPD read code. The
+ * SPD read code has been made generic and moved out of the persimmon
+ * directory, so the ASF init is being done here.
+ */
+ pm_iowrite(0x29, 0x80);
+ pm_iowrite(0x28, 0x61);
}
struct chip_operations mainboard_ops = {