Persimmon/Fam14/SB800 DSDT: Split into common areas

Split the Persimmon DSDT into common code areas.
For example, split the Southbridge specific code into
the Southbridge directory and CPU specific code into
the CPU directory.  Also adding the superio.asl file
to the Persimmon DSDT tree. This file is empty for
the moment but will be necessary in the future.  I have
also emptied the thermal.asl file in the mainboard
directory because it does not seem to perform as
intended (fan control does not change when it is
brought back into the code base) and it has been
inside a '#if 0' statement for a long time.  Removing
it until it is decided that it is actually necessary.

This change was verified in three different ways:
	1. Visual comparison of the compiled DSDT pulled from the
	Persimmon after booting into Linux using the ACPI tools
	acpidump, acpixtract, and iasl.  The comparison was done
	between the DSDT before and after doing the split work.

	This test is somewhat difficult considering the expanse
	of the changes.  Blocks of code have been moved, and
	others changed.

	2. Linux logs were dumped before and after the DSDT split.
	Logs dumped and compared include dmesg and lspci -tv.
	Neither log changed significantly between the two compare
	points.

	3. The test suite FWTS was run on the Coreboot build both
	before and after doing the DSDT split with the command
	'sudo fwts -b -P -u'.  The flag -b specifies all batch jobs,
	-P specifies all power tests, and -u specifies utilities.
	Interactive jobs were not run as most of them consist of
	laptop checks.  Again, there were no significant changes
	between the two endpoints.

These tests lead me to believe that there was no change in
the functionality of the ACPI tables apart from what is
known and expected.

This patch is the first of a series of patches to split the DSDT.
The ASRock patch was merged before this one and breaks the ASROCK
E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/).
Please be aware of this dependency when pulling these patches.
Other patches that depend on this patch are
'AMD Fam14: Split out the AMD Fam14 DSDT'
(http://review.coreboot.org/#/c/3051/)
and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC'
(http://review.coreboot.org/#/c/3052/)

Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>

7 files changed, 337 insertions, 80 deletions

diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl
new file mode 100644
index 0000000000..6ad1ad4d48
--- /dev/null
+++ b/src/mainboard/amd/persimmon/acpi/gpe.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope(\_GPE) {	/* Start Scope GPE */
+
+	/*  General event 3  */
+	Method(_L03) {
+		/* DBGO("\\_GPE\\_L00\n") */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  Legacy PM event  */
+	Method(_L08) {
+		/* DBGO("\\_GPE\\_L08\n") */
+	}
+
+	/*  Temp warning (TWarn) event  */
+	Method(_L09) {
+		/* DBGO("\\_GPE\\_L09\n") */
+		/* Notify (\_TZ.TZ00, 0x80) */
+	}
+
+	/*  USB controller PME#  */
+	Method(_L0B) {
+		/* DBGO("\\_GPE\\_L0B\n") */
+		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  ExtEvent0 SCI event  */
+	Method(_L10) {
+		/* DBGO("\\_GPE\\_L10\n") */
+	}
+
+
+	/*  ExtEvent1 SCI event  */
+	Method(_L11) {
+		/* DBGO("\\_GPE\\_L11\n") */
+	}
+
+	/*  GPIO0 or GEvent8 event  */
+	Method(_L18) {
+		/* DBGO("\\_GPE\\_L18\n") */
+		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  Azalia SCI event  */
+	Method(_L1B) {
+		/* DBGO("\\_GPE\\_L1B\n") */
+		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+} 	/* End Scope GPE */
+
+/* Contains the GPEs for USB overcurrent */
+#include "usb_oc.asl"
+
diff --git a/src/mainboard/amd/persimmon/acpi/mainboard.asl b/src/mainboard/amd/persimmon/acpi/mainboard.asl
new file mode 100644
index 0000000000..49ea44fabf
--- /dev/null
+++ b/src/mainboard/amd/persimmon/acpi/mainboard.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Data to be patched by the BIOS during POST */
+/* FIXME the patching is not done yet! */
+/* Memory related values */
+Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0)	/* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
+Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+Name(SSFG, 0x0D)	/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSTP, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones)	/* Assume nothing */
+Name(PMOD, One)	/* Assume APIC */
+
+Scope(\_SB) {
+	Method(CkOT, 0){
+
+		if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+		if(CondRefOf(\_OSI,Local1))
+		{
+			Store(1, OSTP)					/* Assume some form of XP */
+			if (\_OSI("Windows 2006"))		/* Vista */
+			{
+				Store(2, OSTP)
+			}
+		} else {
+			If(WCMP(\_OS,"Linux")) {
+				Store(3, OSTP)				/* Linux */
+			} Else {
+				Store(4, OSTP)				/* Gotta be WinCE */
+			}
+		}
+		Return(OSTP)
+	}
+}
+
+Scope(\_SI) {
+	Method(_SST, 1) {
+		/* DBGO("\\_SI\\_SST\n") */
+		/* DBGO("   New Indicator state: ") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+	}
+} /* End Scope SI */
+
diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl
index 7a871da047..e98047ce6f 100644
--- a/src/mainboard/amd/persimmon/acpi/routing.asl
+++ b/src/mainboard/amd/persimmon/acpi/routing.asl
@@ -64,37 +64,17 @@ Scope(\_SB) {
 		Package(){0x0007FFFF, 2, INTB, 0 },
 		Package(){0x0007FFFF, 3, INTC, 0 },
 
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
+
 		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
+		/* Bus 0, Dev 17 - SATA controller */
 		Package(){0x0011FFFF, 0, INTD, 0 },
 
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
+		/* OHCI, dev 18, 19, 22 func 0
+		 * EHCI, dev 18, 19, 22 func 2 */
+		Package(){0x0012FFFF, 0, INTC, 0 },	/* Dev 12, INTA, handled by INTC device, Global */
+		Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
 
 		Package(){0x0013FFFF, 0, INTC, 0 },
 		Package(){0x0013FFFF, 1, INTB, 0 },
@@ -102,9 +82,7 @@ Scope(\_SB) {
 		Package(){0x0016FFFF, 0, INTC, 0 },
 		Package(){0x0016FFFF, 1, INTB, 0 },
 
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
 		Package(){0x0014FFFF, 0, INTA, 0 },
 		Package(){0x0014FFFF, 1, INTB, 0 },
 		Package(){0x0014FFFF, 2, INTC, 0 },
@@ -160,34 +138,19 @@ Scope(\_SB) {
 		Package(){0x0007FFFF, 2, 0, 17 },
 		Package(){0x0007FFFF, 3, 0, 18 },
 
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
 		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
 
 		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
+		/* Bus 0, Dev 17 - SATA controller */
 		Package(){0x0011FFFF, 0, 0, 19 },
 
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
+		/* OHCI, dev 18, 19, 22 func 0
+		 * EHCI, dev 18, 19, 22 func 2 */
 		Package(){0x0012FFFF, 0, 0, 18 },
 		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
 
 		Package(){0x0013FFFF, 0, 0, 18 },
 		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
 
 		Package(){0x0016FFFF, 0, 0, 18 },
 		Package(){0x0016FFFF, 1, 0, 17 },
@@ -299,36 +262,6 @@ Scope(\_SB) {
 		Package(){0x0000FFFF, 3, 0, 18 },
 	})
 
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSa, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSa, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
 	Name(PE0, Package(){
 		/* PCIe slot - Hooked to PCIe slot 10 */
 		Package(){0x0000FFFF, 0, INTA, 0 },
@@ -390,7 +323,7 @@ Scope(\_SB) {
 	})
 
 	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
 		Package(){0x0003FFFF, 0, 0, 0x14 },
 		Package(){0x0003FFFF, 1, 0, 0x15 },
 		Package(){0x0003FFFF, 2, 0, 0x16 },
diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl
new file mode 100644
index 0000000000..a109151509
--- /dev/null
+++ b/src/mainboard/amd/persimmon/acpi/sleep.asl
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+*		-none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort	the operation without notification to
+* the ACPI driver.  This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+	/* DBGO("\\_PTS\n") */
+	/* DBGO("From S0 to S") */
+	/* DBGO(Arg0) */
+	/* DBGO("\n") */
+
+	/* Don't allow PCIRST# to reset USB */
+	if (LEqual(Arg0,3)){
+		Store(0,URRE)
+	}
+
+	/* Clear sleep SMI status flag and enable sleep SMI trap. */
+	/*Store(One, CSSM)
+	Store(One, SSEN)*/
+
+	/* On older chips, clear PciExpWakeDisEn */
+	/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+	*    	Store(0,\_SB.PWDE)
+	*}
+	*/
+
+	/* Clear wake status structure. */
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+} /* End Method(\_PTS) */
+
+/*
+*	\_BFS OEM Back From Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		-none-
+*/
+Method(\_BFS, 1) {
+	/* DBGO("\\_BFS\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+}
+
+/*
+*  \_WAK System Wake method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		Return package of 2 DWords
+*		Dword 1 - Status
+*			0x00000000	wake succeeded
+*			0x00000001	Wake was signaled but failed due to lack of power
+*			0x00000002	Wake was signaled but failed due to thermal condition
+*		Dword 2 - Power Supply state
+*			if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+	/* DBGO("\\_WAK\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+
+	/* Re-enable HPET */
+	Store(1,HPDE)
+
+	/* Restore PCIRST# so it resets USB */
+	if (LEqual(Arg0,3)){
+		Store(1,URRE)
+	}
+
+	/* Arbitrarily clear PciExpWakeStatus */
+	Store(PWST, PWST)
+
+	/* if(DeRefOf(Index(WKST,0))) {
+	*	Store(0, Index(WKST,1))
+	* } else {
+	*	Store(Arg0, Index(WKST,1))
+	* }
+	*/
+	Return(WKST)
+} /* End Method(\_WAK) */
+
diff --git a/src/mainboard/amd/persimmon/acpi/superio.asl b/src/mainboard/amd/persimmon/acpi/superio.asl
new file mode 100644
index 0000000000..e042553bee
--- /dev/null
+++ b/src/mainboard/amd/persimmon/acpi/superio.asl
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/amd/persimmon/acpi/thermal.asl b/src/mainboard/amd/persimmon/acpi/thermal.asl
new file mode 100644
index 0000000000..2f50475305
--- /dev/null
+++ b/src/mainboard/amd/persimmon/acpi/thermal.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Thermal Zones have been #if 0 for a long time.
+ * Removing it for now because it doesn't seem to
+ * do anything when enabled anyway.
+ */
diff --git a/src/mainboard/amd/persimmon/acpi/usb.asl b/src/mainboard/amd/persimmon/acpi/usb_oc.asl
index 2822ffda83..0429ac77b2 100644
--- a/src/mainboard/amd/persimmon/acpi/usb.asl
+++ b/src/mainboard/amd/persimmon/acpi/usb_oc.asl
@@ -25,9 +25,22 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
 		#include "usb.asl"
 	}
 */
+
+/* USB overcurrent mapping pins.   */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
+
 Method(UCOC, 0) {
 	Sleep(20)
-    	Store(0x13,CMTI)
+	Store(0x13,CMTI)
 	Store(0,GPSL)
 }
 
@@ -125,7 +138,7 @@ If (LLessEqual(UOM6,9)) {
 
 /* USB Port 7 overcurrent uses Gpm 7 */
 If (LLessEqual(UOM7,9)) {
- 	Scope (\_GPE) {
+	Scope (\_GPE) {
 		/* Method (_L1D) { */
 		Method (_L07) {
 			UCOC()