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| author | Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> | 2022-02-21 20:22:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-09 14:31:02 +0000 |
| commit | ada2a63dabe566b1cb8ebb9d909fa2c07f296136 (patch) | |
| tree | 7ad6339859d63d5c9f692874b5e7ebdcf91e2815 /src/mainboard/amd/parmer/bootblock.c | |
| parent | 6555c4c6017bcd3255611dfef36508cd8e132f65 (diff) | |
soc/mediatek/mt8186: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/parmer/bootblock.c')
0 files changed, 0 insertions, 0 deletions