mainboard/amd: Add padmelon board code

Padmelon board code was written for Merlin Falcon (family 15h models 60h-6fh),
but as the needed binaries are not yet merged (commit 33615), a config
HAVE_MERLINFALCON_BINARIES was added. If the binaries are not available,
the board defaults to Prairie Falcon, which use the same binaries as Stoney
Ridge. Once the binaries are merged, the config will be eliminated. Fan
control is done through F81803A SIO, and IRQ/GPIO and other board
characteristics are the same regardless of Merlin Falcon or Prairie Falcon.

Padmelon board was created to accept Prairie Falcon, Brown Falcon and Merlin
Falcon. The requested development was for Merlin Falcon. There are some small
spec changes (such as number of memory channels) between SOCs. Brown Falcon
was not investigated, Prairie Falcon is very similar to Stoney Ridge.

Started from Gardenia code, added changes created by Marc Jones and finally
revised against schematic, which added changes to GPIO settings.

BUG=none.
TEST=Both versions tested and boot to Linux using SeaBIOS.

Change-Id: I5a366ddeb4cfebd177a8744f6edb87aecd4787dd
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 64 insertions, 0 deletions

diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c
new file mode 100644
index 0000000000..864928732c
--- /dev/null
+++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017-2018 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/southbridge.h>
+#include <amdblocks/lpc.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <drivers/uart/uart8250reg.h>
+#include <arch/io.h>
+#include "../gpio.h"
+
+/* Enable IO access to port, then enable UART HW control pins */
+static void enable_serial(unsigned int base_port, unsigned int io_enable)
+{
+	u32 temp;
+	u8 reg;
+	temp = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE);
+	temp |= io_enable;
+	pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, temp);
+
+	/*
+	 * Remove this section if HW handshake is not needed. This is needed
+	 * only for those who don't have a modified serial cable (connecting
+	 * DCD to DTR and DSR, plus connecting RTS to CTS). When you buy cables
+	 * on any store, they don't have these modification.
+	 */
+	reg = inb(base_port + UART8250_MCR);
+	reg |= UART8250_MCR_DTR | UART8250_MCR_RTS;
+	outb(reg, base_port + UART8250_MCR);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	sb_clk_output_48Mhz(2);
+	/*
+	 * UARTs enabled by default at reset, just need RTS, CTS
+	 * and access to the IO address.
+	 */
+	enable_serial(0x03f8, DECODE_ENABLE_SERIAL_PORT0);
+	enable_serial(0x02f8, DECODE_ENABLE_SERIAL_PORT1);
+}
+
+void bootblock_mainboard_init(void)
+{
+	size_t num_gpios;
+	const struct soc_amd_gpio *gpios;
+
+	gpios = early_gpio_table(&num_gpios);
+	program_gpios(gpios, num_gpios);
+}