mb/amd/padmelon: rename to pademelon

This AMD reference board is called Pademelon and not Padmelon, so fix
the name in coreboot. Also update the corresponding documentation.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

4 files changed, 296 insertions, 0 deletions

diff --git a/src/mainboard/amd/pademelon/acpi/gpe.asl b/src/mainboard/amd/pademelon/acpi/gpe.asl
new file mode 100644
index 0000000000..96a221e5b9
--- /dev/null
+++ b/src/mainboard/amd/pademelon/acpi/gpe.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+External (\_SB.PCI0.AZHD, DeviceObj)
+
+Scope(\_GPE) {	/* Start Scope GPE */
+
+	/*  General event 3  */
+	Method(_L03) {
+		/*  DBGO("\\_GPE\\_L03\n") */
+		Notify(\_SB.PWRB, 0x02) /* SIO psin -> NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  Power Button - PCIe Wake */
+	Method(_L08) {
+		/*  DBGO("\\_GPE\\_L08\n") */
+		\_SB.SIO0.CPSI() /*  clear psin state in sio */
+		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR8, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+}	/* End Scope GPE */
diff --git a/src/mainboard/amd/pademelon/acpi/routing.asl b/src/mainboard/amd/pademelon/acpi/routing.asl
new file mode 100644
index 0000000000..de6ff3d92f
--- /dev/null
+++ b/src/mainboard/amd/pademelon/acpi/routing.asl
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+	/* NB devices */
+	/* Bus 0, Dev 0 - F15 Host Controller */
+
+	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+	Package(){0x0001FFFF, 0, INTB, 0 },
+	Package(){0x0001FFFF, 1, INTC, 0 },
+
+	/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
+	Package(){0x0002FFFF, 0, INTC, 0 },
+	Package(){0x0002FFFF, 1, INTD, 0 },
+	Package(){0x0002FFFF, 2, INTA, 0 },
+	Package(){0x0002FFFF, 3, INTB, 0 },
+
+	/* FCH devices */
+	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+	Package(){0x0014FFFF, 0, INTA, 0 },
+	Package(){0x0014FFFF, 1, INTB, 0 },
+	Package(){0x0014FFFF, 2, INTC, 0 },
+	Package(){0x0014FFFF, 3, INTD, 0 },
+
+	/* Bus 0, Dev 18 Func 0 - USB: EHCI */
+	Package(){0x0012FFFF, 0, INTC, 0 },
+	Package(){0x0012FFFF, 1, INTB, 0 },
+
+	/* Bus 0, Dev 16 Func 0 - USB: xHCI */
+	Package(){0x0010FFFF, 0, INTC, 0 },
+	Package(){0x0010FFFF, 1, INTB, 0 },
+
+	/* Bus 0, Dev 17 - SATA controller */
+	Package(){0x0011FFFF, 0, INTD, 0 },
+})
+
+Name(APR0, Package(){
+	/* NB devices in APIC mode */
+	/* Bus 0, Dev 0 - F15 Host Controller */
+
+	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+	Package(){0x0001FFFF, 0, 0, 43 },
+	Package(){0x0001FFFF, 1, 0, 40 },
+
+	/* Bus 0, Dev 2 - PCIe Bridges  */
+	Package(){0x0002FFFF, 0, 0, 44 },
+	Package(){0x0002FFFF, 1, 0, 45 },
+	Package(){0x0002FFFF, 2, 0, 46 },
+	Package(){0x0002FFFF, 3, 0, 47 },
+
+	Package(){0x0003FFFF, 0, 0, 49 },
+	Package(){0x0003FFFF, 1, 0, 50 },
+	Package(){0x0003FFFF, 2, 0, 51 },
+	Package(){0x0003FFFF, 3, 0, 52 },
+
+	Package(){0x0008FFFF, 0, 0, 35 },
+	Package(){0x0008FFFF, 1, 0, 32 },
+	Package(){0x0008FFFF, 2, 0, 33 },
+	Package(){0x0008FFFF, 3, 0, 34 },
+
+	/* SB devices in APIC mode */
+	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+	Package(){0x0014FFFF, 0, 0, 16 },
+	Package(){0x0014FFFF, 1, 0, 17 },
+	Package(){0x0014FFFF, 2, 0, 18 },
+	Package(){0x0014FFFF, 3, 0, 19 },
+
+	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
+	Package(){0x0012FFFF, 0, 0, 18 },
+	Package(){0x0012FFFF, 1, 0, 17 },
+
+	Package(){0x0013FFFF, 0, 0, 18 },
+	Package(){0x0013FFFF, 1, 0, 17 },
+
+	/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+	Package(){0x0010FFFF, 0, 0, 18},
+	Package(){0x0010FFFF, 1, 0, 17},
+
+	/* Bus 0, Dev 17 - SATA controller */
+	Package(){0x0011FFFF, 0, 0, 19 },
+
+	/* Bus 0, Dev 9, Func 2 - HDAudio */
+	Package(){0x0009FFFF, 0, 0, 46 },
+	Package(){0x0009FFFF, 1, 0, 47 },
+	Package(){0x0009FFFF, 2, 0, 44 },
+	Package(){0x0009FFFF, 3, 0, 45 },
+})
+
+Name(PS4, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+	/* PCIe slot - Hooked to PCIe slot 4 */
+	Package(){0x0000FFFF, 0, 0, 24 },
+	Package(){0x0000FFFF, 1, 0, 25 },
+	Package(){0x0000FFFF, 2, 0, 26 },
+	Package(){0x0000FFFF, 3, 0, 27 },
+})
+
+/* GPP 1 */
+Name(PS5, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS5, Package(){
+	Package(){0x0000FFFF, 0, 0, 32 },
+	Package(){0x0000FFFF, 1, 0, 33 },
+	Package(){0x0000FFFF, 2, 0, 34 },
+	Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 2 */
+Name(PS6, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS6, Package(){
+	Package(){0x0000FFFF, 0, 0, 40 },
+	Package(){0x0000FFFF, 1, 0, 41 },
+	Package(){0x0000FFFF, 2, 0, 42 },
+	Package(){0x0000FFFF, 3, 0, 43 },
+})
+
+/* GPP 3 */
+Name(PS7, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS7, Package(){
+	Package(){0x0000FFFF, 0, 0, 48 },
+	Package(){0x0000FFFF, 1, 0, 49 },
+	Package(){0x0000FFFF, 2, 0, 50 },
+	Package(){0x0000FFFF, 3, 0, 51 },
+})
+
+/* GPP 4 */
+Name(PS8, Package(){
+	Package(){0x0000FFFF, 0, INTD, 0 },
+	Package(){0x0000FFFF, 1, INTA, 0 },
+	Package(){0x0000FFFF, 2, INTB, 0 },
+	Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS8, Package(){
+	Package(){0x0000FFFF, 0, 0, 27 },
+	Package(){0x0000FFFF, 1, 0, 28 },
+	Package(){0x0000FFFF, 2, 0, 28 },
+	Package(){0x0000FFFF, 3, 0, 30 },
+})
+
+/* GFX 2 */
+Name(PSA, Package(){
+	Package(){0x0000FFFF, 0, INTD, 0 },
+	Package(){0x0000FFFF, 1, INTA, 0 },
+	Package(){0x0000FFFF, 2, INTB, 0 },
+	Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APSA, Package(){
+	Package(){0x0000FFFF, 0, 0, 51 },
+	Package(){0x0000FFFF, 1, 0, 48 },
+	Package(){0x0000FFFF, 2, 0, 49 },
+	Package(){0x0000FFFF, 3, 0, 50 },
+})
+
+/* GFX 3 */
+Name(PSB, Package(){
+	Package(){0x0000FFFF, 0, INTC, 0 },
+	Package(){0x0000FFFF, 1, INTD, 0 },
+	Package(){0x0000FFFF, 2, INTA, 0 },
+	Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APSB, Package(){
+	Package(){0x0000FFFF, 0, 0, 26 },
+	Package(){0x0000FFFF, 1, 0, 27 },
+	Package(){0x0000FFFF, 2, 0, 24 },
+	Package(){0x0000FFFF, 3, 0, 25 },
+})
+
+/* GFX 4 */
+Name(PSC, Package(){
+	Package(){0x0000FFFF, 0, INTC, 0 },
+	Package(){0x0000FFFF, 1, INTD, 0 },
+	Package(){0x0000FFFF, 2, INTA, 0 },
+	Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APSC, Package(){
+	Package(){0x0000FFFF, 0, 0, 34 },
+	Package(){0x0000FFFF, 1, 0, 35 },
+	Package(){0x0000FFFF, 2, 0, 32 },
+	Package(){0x0000FFFF, 3, 0, 33 },
+})
diff --git a/src/mainboard/amd/pademelon/acpi/sleep.asl b/src/mainboard/amd/pademelon/acpi/sleep.asl
new file mode 100644
index 0000000000..0cbf8e3211
--- /dev/null
+++ b/src/mainboard/amd/pademelon/acpi/sleep.asl
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+*		-none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method.  This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver.  This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(_PTS, 1) {
+	/* DBGO("\\_PTS\n") */
+	/* DBGO("From S0 to S") */
+	/* DBGO(Arg0) */
+	/* DBGO("\n") */
+
+	/* Clear wake status structure. */
+	PEWD = 0
+	WKST [0] = 0
+	WKST [1] = 0
+	UPWS = 7
+} /* End Method(\_PTS) */
+
+/*
+*  \_WAK System Wake method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		Return package of 2 DWords
+*		Dword 1 - Status
+*			0x00000000	wake succeeded
+*			0x00000001	Wake was signaled but failed due to lack of power
+*			0x00000002	Wake was signaled but failed due to thermal condition
+*		Dword 2 - Power Supply state
+*			if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+	/* DBGO("\\_WAK\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+
+	Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/pademelon/acpi/usb_oc.asl b/src/mainboard/amd/pademelon/acpi/usb_oc.asl
new file mode 100644
index 0000000000..a5846fe848
--- /dev/null
+++ b/src/mainboard/amd/pademelon/acpi/usb_oc.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* USB overcurrent mapping pins.   */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)