diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-11-21 17:40:37 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-03 08:08:18 +0100 |
| commit | 88ff8b541f0981359ce17021e9b41d57c6eb427b (patch) | |
| tree | d16b06d0e01d149f0fa2809c1a4c0bf48992496a /src/mainboard/amd/olivehill | |
| parent | 8c20a04cae5bcd15f289550eec0dcb2626ac5ce4 (diff) | |
AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port
Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.
Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7602
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/amd/olivehill')
| -rw-r--r-- | src/mainboard/amd/olivehill/agesawrapper.c | 7 | ||||
| -rw-r--r-- | src/mainboard/amd/olivehill/romstage.c | 4 |
2 files changed, 4 insertions, 7 deletions
diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index 22522db291..242aa27b2f 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 0a982b6fe8..1ff7a0b084 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -53,6 +53,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { |