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authorSubrata Banik <subrata.banik@intel.com>2021-07-30 17:36:56 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-08-16 05:07:12 +0000
commit0e2510f616bc8a23428bd5eec97aaa698948c666 (patch)
treebb30d916eadcdc49da14435dee6b084371f97bb5 /src/mainboard/amd/olivehill/devicetree.cb
parentad08265740cecef94bf7fd895221aceb0fcd28b7 (diff)
soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC Kconfig and here is modified flow as below: Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS Update eNEM init flow: - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1 Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000 BUG=b:168820083 TEST=Verified filling up the entire cache with memcpy at the beginning itself and then running the entire bootblock, verstage, debug FSP-M without running into any issue. This proves that code caching and eviction is working as expected in eNEM mode. Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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