AMD Norwich: minor cosmetic fixes and drop dead code (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 31 insertions, 41 deletions

diff --git a/src/mainboard/amd/norwich/mainboard.c b/src/mainboard/amd/norwich/mainboard.c
index 9d957eb852..14b8392eb9 100644
--- a/src/mainboard/amd/norwich/mainboard.c
+++ b/src/mainboard/amd/norwich/mainboard.c
@@ -14,7 +14,7 @@
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
-* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	 02110-1301 USA
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 
 #include <console/console.h>
@@ -26,7 +26,9 @@
 #include "../../../southbridge/amd/cs5536/cs5536.h"
 #include "chip.h"
 
-/* Print the platform configuration - do before PCI init or it will not work right */
+/* Print the platform configuration - do before PCI init or it will not
+ * work right.
+ */
 void print_conf(void)
 {
 #if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
@@ -34,61 +36,49 @@ void print_conf(void)
 	unsigned long iol;
 	msr_t msr;
 
-	int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
-		CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
-		CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF,
-		    CPU_RCONF_E0_FF,
-		CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
+	int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
+		CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
+		CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
+		GLCP_DELAY_CONTROLS, GL_END
 	};
 
-	int gliu0_msr_defs[] =
-	    { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4,
- MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
+	int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
+		MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
 		GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
 		GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
-		    MSR_GLIU0_SHADOW,
-		GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
-		GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3,
-		    GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
+		MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
+		GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
+		GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
 		GLIU0_GLD_MSR_COH, GL_END
 	};
 
-	int gliu1_msr_defs[] =
-	    { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3,
- MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
-		MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9,
-		    MSR_GLIU1_BASE10,
-		GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3,
-		    MSR_GLIU1_SHADOW,
-		GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
-		GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
+	int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
+		MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
+		MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
+		MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
+		GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
+		GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
+		GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
 		GLIU1_GLD_MSR_COH, GL_END
 	};
 
-	int rconf_msr[] =
-	    { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
-		CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
+	int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
+		CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
 	};
 
-	int cs5536_msr[] =
-	    { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO,
-     MDD_PIN_OPT,
-		MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
+	int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
+		MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
+		MDD_IRQM_PRIM, GL_END
 	};
 
-	int pci_msr[] =
-	    { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF,
-	GLPCI_E0_FF,
-		GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR,
-		    GLPCI_SPARE,
-		GL_END
+	int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
+		GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
+		GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
 	};
 
-	int dma_msr[] =
-	    { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3,
-	MDD_DMA_SHAD4,
-		MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
-		MDD_DMA_SHAD9, GL_END
+	int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
+		MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
+		MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
 	};
 
 	printk_debug("---------- CPU ------------\n");