diff options
| author | Jordan Crouse <jordan.crouse@amd.com> | 2007-05-10 18:00:24 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2007-05-10 18:00:24 +0000 |
| commit | 89d7cd2c833245078d917bf7d85b3a7ba4fd6c03 (patch) | |
| tree | b217a18e4704b3d33a18149d4250eb4a33e306a8 /src/mainboard/amd/norwich/cache_as_ram_auto.c | |
| parent | 4fcb3ba93f483e194630710f61edde6572b2dc70 (diff) | |
Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/norwich/cache_as_ram_auto.c')
| -rw-r--r-- | src/mainboard/amd/norwich/cache_as_ram_auto.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/amd/norwich/cache_as_ram_auto.c b/src/mainboard/amd/norwich/cache_as_ram_auto.c index b15f6aabdf..3b87c5e414 100644 --- a/src/mainboard/amd/norwich/cache_as_ram_auto.c +++ b/src/mainboard/amd/norwich/cache_as_ram_auto.c @@ -42,11 +42,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ +#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRlo 0x02000030 #define DIMM0 0xA0 #define DIMM1 0xA2 @@ -62,11 +62,11 @@ static void msr_init(void) msr_t msr; /* Setup access to the cache for under 1MB. */ msr.hi = 0x24fffc02; - msr.lo = 0x1000A000; /* 0-A0000 write back */ + msr.lo = 0x1000A000; /* 0-A0000 write back */ wrmsr(CPU_RCONF_DEFAULT, msr); - msr.hi = 0x0; /* write back */ - msr.lo = 0x0; + msr.hi = 0x0; /* write back */ + msr.lo = 0x0; wrmsr(CPU_RCONF_A0_BF, msr); wrmsr(CPU_RCONF_C0_DF, msr); wrmsr(CPU_RCONF_E0_FF, msr); @@ -81,11 +81,11 @@ static void msr_init(void) wrmsr(MSR_GLIU0 + 0x21, msr); msr.hi = 0x20000000; - msr.lo = 0xfff80; + msr.lo = 0xfff80; wrmsr(MSR_GLIU1 + 0x20, msr); msr.hi = 0x20000000; - msr.lo = 0x80fffe0; + msr.lo = 0x80fffe0; wrmsr(MSR_GLIU1 + 0x21, msr); } @@ -99,8 +99,8 @@ void cache_as_ram_main(void) { POST_CODE(0x01); - static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} }; SystemPreInit(); @@ -112,8 +112,8 @@ void cache_as_ram_main(void) * it is counting on some early MSR setup * for cs5536 */ - /* cs5536_disable_internal_uart disable them for now, set them up later...*/ - cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ + /* cs5536_disable_internal_uart disable them for now, set them up later... */ + cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ mb_gpio_init(); uart_init(); console_init(); @@ -125,7 +125,7 @@ void cache_as_ram_main(void) sdram_initialize(1, memctrl); /* Check all of memory */ - /*ram_check(0x00000000, 640*1024);*/ + /*ram_check(0x00000000, 640*1024); */ /* Memory is setup. Return to cache_as_ram.inc and continue to boot */ return; |