diff options
author | Marc Jones <marc.jones@amd.com> | 2007-05-04 18:47:52 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2007-05-04 18:47:52 +0000 |
commit | 9c9083ba4a1cd280fe70c0eec78e562d714a2dc7 (patch) | |
tree | 690f8bc96d2598fce87cbd2f36557d1ebf5f88ae /src/mainboard/amd/norwich/cache_as_ram_auto.c | |
parent | bc8176c5526ec9124aa99559f9432210be364dfe (diff) |
This patch adds support for the AMD Norwich development platform
based on the Geode LX processor. The Norwich is the canonical
Geode reference, and will server as a good basis for other
Geode based platforms.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/norwich/cache_as_ram_auto.c')
-rw-r--r-- | src/mainboard/amd/norwich/cache_as_ram_auto.c | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/src/mainboard/amd/norwich/cache_as_ram_auto.c b/src/mainboard/amd/norwich/cache_as_ram_auto.c new file mode 100644 index 0000000000..59b651fd56 --- /dev/null +++ b/src/mainboard/amd/norwich/cache_as_ram_auto.c @@ -0,0 +1,118 @@ +/* +* +* Copyright (C) 2007 Advanced Micro Devices +* +*/ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" + +#define POST_CODE(x) outb(x, 0x80) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define ManualConf 0 /* Do automatic strapped PLL config */ +#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ +#define PLLMSRlo 0x02000030 +#define DIMM0 0xA0 +#define DIMM1 0xA2 +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "sdram/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +static void msr_init(void) +{ + msr_t msr; + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); + +} + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +void cache_as_ram_main(void) +{ + POST_CODE(0x01); + + static const struct mem_controller memctrl [] = { + {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536 + */ + /* cs5536_disable_internal_uart disable them for now, set them up later...*/ + cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* Check all of memory */ + /*ram_check(0x00000000, 640*1024);*/ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot */ + return; +} |