diff options
| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2020-04-04 05:27:05 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-21 01:17:31 +0000 |
| commit | e6315f74d6f402734e476a57a8faf4ac9cb23d38 (patch) | |
| tree | 21ef786a292ad9ec95bbbb196d9234588d6ffa97 /src/mainboard/amd/mandolin/bootblock.c | |
| parent | 12b0f7746e6ce8c3eeb677e093b756aeb8ede493 (diff) | |
mb/amd/mandolin: Add Picasso CRB
Mandolin is the CRB for AMD Picasso and Dali.
The mainboard code still needs a little cleanup and verification, but
I'll do that in a follow-up to have a non Chromebook board using the
Picasso SoC code in tree as soon as possible to be able to detect some
possible breakage.
BUG=b:130660285
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33772
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/mandolin/bootblock.c')
| -rw-r--r-- | src/mainboard/amd/mandolin/bootblock.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/amd/mandolin/bootblock.c b/src/mainboard/amd/mandolin/bootblock.c new file mode 100644 index 0000000000..06da379d93 --- /dev/null +++ b/src/mainboard/amd/mandolin/bootblock.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <amdblocks/lpc.h> +#include <superio/smsc/sio1036/sio1036.h> +#include "gpio.h" + +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) + +void bootblock_mainboard_early_init(void) +{ + mainboard_program_early_gpios(); + + if (CONFIG(SUPERIO_SMSC_SIO1036)) { + lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); + lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE); + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + } +} |