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authorZheng Bao <fishbaozi@gmail.com>2021-01-27 15:48:35 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-03-03 18:39:27 +0000
commit2494aa952c911c64113581fcd6895a9222973c72 (patch)
tree88423b9238227577cd14162339f7a945a126fb74 /src/mainboard/amd/majolica
parentb2f3151ed96228a3d4aa7bbbd78c2414f2322bf8 (diff)
mb/amd/majolica: Add eSPI support
Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/amd/majolica')
-rw-r--r--src/mainboard/amd/majolica/Kconfig1
-rw-r--r--src/mainboard/amd/majolica/devicetree.cb12
2 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig
index 6f3f93ba30..26cae008c3 100644
--- a/src/mainboard/amd/majolica/Kconfig
+++ b/src/mainboard/amd/majolica/Kconfig
@@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select SOC_AMD_CEZANNE
+ select SOC_AMD_COMMON_BLOCK_USE_ESPI
select AMD_SOC_CONSOLE_UART
select MAINBOARD_HAS_CHROMEOS
diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb
index 2695f60cef..195120baea 100644
--- a/src/mainboard/amd/majolica/devicetree.cb
+++ b/src/mainboard/amd/majolica/devicetree.cb
@@ -1,6 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only
chip soc/amd/cezanne
+ register "common_config.espi_config" = "{
+ .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN | ESPI_DECODE_IO_0x80_EN,
+
+ .io_mode = ESPI_IO_MODE_QUAD,
+ .op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
+ .crc_check_enable = 1,
+ .dedicated_alert_pin = 1,
+ .periph_ch_en = 1,
+ .vw_ch_en = 1,
+ .oob_ch_en = 1,
+ .flash_ch_en = 0,
+ }"
device domain 0 on
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A