diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-02-26 10:11:21 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-08 04:08:00 +0100 |
| commit | 1b183aa6ce78af27c2e42aa51626f76a4b5d5bb0 (patch) | |
| tree | 8148c084ef3cdbc6ed86972694864ef910d6668e /src/mainboard/amd/lamar | |
| parent | 3444a9d716ba52f9bd8fb03870442ab1ce1654cf (diff) | |
binaryPI boards: Drop any ACPI S3 support
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/amd/lamar')
| -rw-r--r-- | src/mainboard/amd/lamar/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/amd/lamar/romstage.c | 31 |
2 files changed, 8 insertions, 30 deletions
diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 25e685b1b8..4e010fc881 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -147,12 +146,6 @@ static void pirq_setup(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. - */ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index bda8c0fe61..5530a25e84 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -32,7 +31,6 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include "cbmem.h" #include "superio/fintek/f81216h/f81216h.h" @@ -88,29 +86,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } - else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); + post_code(0x40); + AGESAWRAPPER(amdinitpost); - post_code(0x61); - prepare_for_resume(); - } + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); post_code(0x50); copy_and_run(); |