Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.

This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

34 files changed, 7255 insertions, 0 deletions

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
new file mode 100644
index 0000000000..7dcdd96098
--- /dev/null
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -0,0 +1,662 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "SB800.h"
+
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
+{
+  {AGESA_ALLOCATE_BUFFER,
+   BiosAllocateBuffer
+  },
+
+  {AGESA_DEALLOCATE_BUFFER,
+   BiosDeallocateBuffer
+  },
+
+  {AGESA_DO_RESET,
+   BiosReset
+  },
+
+  {AGESA_LOCATE_BUFFER,
+   BiosLocateBuffer
+  },
+
+  {AGESA_READ_SPD,
+   BiosReadSpd
+  },
+
+  {AGESA_READ_SPD_RECOVERY,
+   BiosDefaultRet
+  },
+
+  {AGESA_RUNFUNC_ONAP,
+   BiosRunFuncOnAp
+  },
+
+  {AGESA_GET_IDS_INIT_DATA,
+   BiosGetIdsInitData
+  },
+  
+  {AGESA_HOOKBEFORE_DQS_TRAINING,
+   BiosHookBeforeDQSTraining
+  },
+  
+  {AGESA_HOOKBEFORE_DRAM_INIT,
+   BiosHookBeforeDramInit
+  },
+  {AGESA_HOOKBEFORE_EXIT_SELF_REF,
+   BiosHookBeforeExitSelfRefresh
+  },
+  {AGESA_GNB_PCIE_SLOT_RESET,
+   BiosGnbPcieSlotReset
+  },
+};
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  UINTN i;
+  AGESA_STATUS CalloutStatus;
+
+  for (i = 0; i < REQUIRED_CALLOUTS; i++)
+  {
+    if (BiosCallouts[i].CalloutName == Func)
+    {
+      break;
+    }
+  }
+
+  if(i >= REQUIRED_CALLOUTS)
+  {
+    return AGESA_UNSUPPORTED;
+  }
+
+  CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+  return CalloutStatus;
+}
+
+
+CONST IDS_NV_ITEM IdsData[] =
+{
+  /*{
+    AGESA_IDS_NV_MAIN_PLL_CON,
+    0x1
+  },
+  {
+    AGESA_IDS_NV_MAIN_PLL_FID_EN,
+    0x1
+  },
+  {
+    AGESA_IDS_NV_MAIN_PLL_FID,
+    0x8
+  },
+
+  {
+    AGESA_IDS_NV_CUSTOM_NB_PSTATE,
+  },
+  {
+    AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
+  },
+  {
+    AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
+  },
+  {
+    AGESA_IDS_NV_FORCE_NB_PSTATE,
+  },
+*/
+  {
+    0xFFFF,
+    0xFFFF
+  }
+};
+
+#define   NUM_IDS_ENTRIES    (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
+
+
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  UINTN   i;
+  IDS_NV_ITEM *IdsPtr;
+
+  IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+
+  if (Data == IDS_CALLOUT_INIT) {
+    for (i = 0; i < NUM_IDS_ENTRIES; i++) {
+      IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
+      IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  UINT32              AvailableHeapSize;
+  UINT8               *BiosHeapBaseAddr;
+  UINT32              CurrNodeOffset;
+  UINT32              PrevNodeOffset;
+  UINT32              FreedNodeOffset;
+  UINT32              BestFitNodeOffset;
+  UINT32              BestFitPrevNodeOffset;
+  UINT32              NextFreeOffset;
+  BIOS_BUFFER_NODE   *CurrNodePtr;
+  BIOS_BUFFER_NODE   *FreedNodePtr;
+  BIOS_BUFFER_NODE   *BestFitNodePtr;
+  BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
+  BIOS_BUFFER_NODE   *NextFreePtr;
+  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+  AGESA_BUFFER_PARAMS *AllocParams;
+
+  AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+  AllocParams->BufferPointer = NULL;
+
+  AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+  if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+    /* First allocation */
+    CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+    CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+    CurrNodePtr->BufferSize = AllocParams->BufferLength;
+    CurrNodePtr->NextNodeOffset = 0;
+    AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+    /* Update the remaining free space */
+    FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+    FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+    FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+    FreedNodePtr->NextNodeOffset = 0;
+
+    /* Update the offsets for Allocated and Freed nodes */
+    BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+    BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+  } else {
+    /* Find out whether BufferHandle has been allocated on the heap. */
+    /* If it has, return AGESA_BOUNDS_CHK */
+    CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+    while (CurrNodeOffset != 0) {
+      CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+      if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+        return AGESA_BOUNDS_CHK;
+      }
+      CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+      /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+       to the end of the allocated nodes list.
+      */
+       
+    }
+    /* Find the node that best fits the requested buffer size */
+    FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+    PrevNodeOffset = FreedNodeOffset;
+    BestFitNodeOffset = 0;
+    BestFitPrevNodeOffset = 0;
+    while (FreedNodeOffset != 0) {
+      FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+      if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+        if (BestFitNodeOffset == 0) {
+          /* First node that fits the requested buffer size */
+          BestFitNodeOffset = FreedNodeOffset;
+          BestFitPrevNodeOffset = PrevNodeOffset;
+        } else {
+          /* Find out whether current node is a better fit than the previous nodes */
+          BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+          if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+            BestFitNodeOffset = FreedNodeOffset;
+            BestFitPrevNodeOffset = PrevNodeOffset;
+          }
+        }
+      }
+      PrevNodeOffset = FreedNodeOffset;
+      FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+    } /* end of while loop */
+
+
+    if (BestFitNodeOffset == 0) {
+      /* If we could not find a node that fits the requested buffer */
+      /* size, return AGESA_BOUNDS_CHK */
+      return AGESA_BOUNDS_CHK;
+    } else {
+      BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+      BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+      /* If BestFitNode is larger than the requested buffer, fragment the node further */
+      if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+        NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+        NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+        NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+        NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+      } else {
+        /* Otherwise, next free node is NextNodeOffset of BestFitNode */
+        NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+      }
+
+      /* If BestFitNode is the first buffer in the list, then update
+         StartOfFreedNodes to reflect the new free node
+      */         
+      if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+        BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+      } else {
+        BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+      }
+
+      /* Add BestFitNode to the list of Allocated nodes */
+      CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+      BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+      BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+      BestFitNodePtr->NextNodeOffset = 0;
+
+      /* Remove BestFitNode from list of Freed nodes */
+      AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+  UINT8               *BiosHeapBaseAddr;
+  UINT32              AllocNodeOffset;
+  UINT32              PrevNodeOffset;
+  UINT32              NextNodeOffset;
+  UINT32              FreedNodeOffset;
+  UINT32              EndNodeOffset;
+  BIOS_BUFFER_NODE   *AllocNodePtr;
+  BIOS_BUFFER_NODE   *PrevNodePtr;
+  BIOS_BUFFER_NODE   *FreedNodePtr;
+  BIOS_BUFFER_NODE   *NextNodePtr;
+  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+  AGESA_BUFFER_PARAMS *AllocParams;
+
+  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+  /* Find target node to deallocate in list of allocated nodes.
+     Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+  */
+  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+  PrevNodeOffset = AllocNodeOffset;
+
+  while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
+    if (AllocNodePtr->NextNodeOffset == 0) {
+      return AGESA_BOUNDS_CHK;
+    }
+    PrevNodeOffset = AllocNodeOffset;
+    AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+    AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+  }
+
+  /* Remove target node from list of allocated nodes */
+  PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+  PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+  /* Zero out the buffer, and clear the BufferHandle */
+  LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+  AllocNodePtr->BufferHandle = 0;
+  AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+  /* Add deallocated node in order to the list of freed nodes */
+  FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+  FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+  EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+  if (AllocNodeOffset < FreedNodeOffset) {
+    /* Add to the start of the freed list */
+    if (EndNodeOffset == FreedNodeOffset) {
+      /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+      AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+      AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+      /* Clear the BufferSize and NextNodeOffset of the previous first node */
+      FreedNodePtr->BufferSize = 0;
+      FreedNodePtr->NextNodeOffset = 0;
+
+    } else {
+      /* Otherwise, add freed node to the start of the list 
+         Update NextNodeOffset and BufferSize to include the 
+         size of BIOS_BUFFER_NODE
+      */   
+      AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+    }
+    /* Update StartOfFreedNodes to the new first node */
+    BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+  } else {
+    /* Traverse list of freed nodes to find where the deallocated node
+       should be place
+    */   
+    NextNodeOffset = FreedNodeOffset;
+    NextNodePtr = FreedNodePtr;
+    while (AllocNodeOffset > NextNodeOffset) {
+      PrevNodeOffset = NextNodeOffset;
+      if (NextNodePtr->NextNodeOffset == 0) {
+        break;
+      }
+      NextNodeOffset = NextNodePtr->NextNodeOffset;
+      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+    }
+
+    /* If deallocated node is adjacent to the next node,
+       concatenate both nodes
+    */   
+    if (NextNodeOffset == EndNodeOffset) {
+      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+      AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+      AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+      NextNodePtr->BufferSize = 0;
+      NextNodePtr->NextNodeOffset = 0;
+    } else {
+      /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+      AllocNodePtr->NextNodeOffset = NextNodeOffset;
+    }
+    /* If deallocated node is adjacent to the previous node,
+       concatenate both nodes
+    */   
+    PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+    EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+    if (AllocNodeOffset == EndNodeOffset) {
+      PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+      PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+      AllocNodePtr->BufferSize = 0;
+      AllocNodePtr->NextNodeOffset = 0;
+    } else {
+      PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  UINT32              AllocNodeOffset;
+  UINT8               *BiosHeapBaseAddr;
+  BIOS_BUFFER_NODE   *AllocNodePtr;
+  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+  AGESA_BUFFER_PARAMS *AllocParams;
+
+  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+  while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+    if (AllocNodePtr->NextNodeOffset == 0) {
+      AllocParams->BufferPointer = NULL;
+      AllocParams->BufferLength = 0;
+      return AGESA_BOUNDS_CHK;
+    } else {
+      AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+      AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+    }
+  }
+
+  AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+  AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+  return AGESA_SUCCESS;
+
+}
+
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS        Status;
+
+  Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+  return Status;
+}
+
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS        Status;
+  UINT8                 Value;
+  UINTN               ResetType;
+  AMD_CONFIG_PARAMS   *StdHeader;
+  
+  ResetType = Data;
+  StdHeader = ConfigPtr;
+    
+  //
+  // Perform the RESET based upon the ResetType. In case of
+  // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+  // AmdResetManager. During the critical condition, where reset is required
+  // immediately, the reset will be invoked directly by writing 0x04 to port
+  // 0xCF9 (Reset Port).
+  //
+  switch (ResetType) {
+  case WARM_RESET_WHENEVER:
+  case COLD_RESET_WHENEVER:
+    break;
+    
+  case WARM_RESET_IMMEDIATELY:
+  case COLD_RESET_IMMEDIATELY:
+      Value = 0x06;
+      LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+    break;
+    
+  default:
+    break;
+  }
+  
+  Status = 0;
+  return Status;
+}
+
+AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS Status;
+  Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+
+  return Status;
+}
+
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  return AGESA_UNSUPPORTED;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  return AGESA_SUCCESS;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS      Status;
+  UINTN             FcnData;
+  MEM_DATA_STRUCT   *MemData;
+  UINT32            AcpiMmioAddr;
+  UINT32            GpioMmioAddr;
+  UINT8             Data8;
+  UINT16            Data16;
+  UINT8             TempData8;
+    
+  FcnData = Data;
+  MemData = ConfigPtr;
+  
+  Status  = AGESA_SUCCESS;
+  /* Get SB800 MMIO Base (AcpiMmioAddr) */
+  WriteIo8 (0xCD6, 0x27);
+  Data8   = ReadIo8(0xCD7);
+  Data16  = Data8<<8;
+  WriteIo8 (0xCD6, 0x26);
+  Data8   = ReadIo8(0xCD7);
+  Data16  |= Data8;
+  AcpiMmioAddr = (UINT32)Data16 << 16;
+  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+  
+  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+  Data8 &= ~BIT5;
+  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+  TempData8 &= 0x03;
+  TempData8 |= Data8;
+  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+   
+  Data8 |= BIT2+BIT3;
+  Data8 &= ~BIT4;
+  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+  TempData8 &= 0x23;
+  TempData8 |= Data8;
+  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+  Data8 &= ~BIT5;
+  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+  TempData8 &= 0x03;
+  TempData8 |= Data8;
+  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+  Data8 |= BIT2+BIT3;
+  Data8 &= ~BIT4;
+  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+  TempData8 &= 0x23;
+  TempData8 |= Data8;
+  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+  
+  switch(MemData->ParameterListPtr->DDR3Voltage){
+    case VOLT1_35:
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+      Data8 &= ~(UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+      Data8 |= (UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+      break;
+    case VOLT1_25:
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+      Data8 &= ~(UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+      Data8 &= ~(UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+      break;
+    case VOLT1_5:
+    default:
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+      Data8 |= (UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+      Data8 &= ~(UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+  }
+  return Status;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  return AGESA_SUCCESS;
+}
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS Status;
+  UINTN                 FcnData;
+  PCIe_SLOT_RESET_INFO  *ResetInfo;
+  
+  UINT32  GpioMmioAddr;
+  UINT32  AcpiMmioAddr;
+  UINT8   Data8;
+  UINT16  Data16;
+  
+  FcnData   = Data;
+  ResetInfo = ConfigPtr;
+  // Get SB800 MMIO Base (AcpiMmioAddr)
+  WriteIo8(0xCD6, 0x27);
+  Data8 = ReadIo8(0xCD7);
+  Data16=Data8<<8;
+  WriteIo8(0xCD6, 0x26);
+  Data8 = ReadIo8(0xCD7);
+  Data16|=Data8;
+  AcpiMmioAddr = (UINT32)Data16 << 16;
+  Status = AGESA_UNSUPPORTED;
+  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+  switch (ResetInfo->ResetId)
+  {
+  case 4:
+      switch (ResetInfo->ResetControl)
+      {
+      case AssertSlotReset:
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+        Data8 &= ~(UINT8)BIT6 ; 
+        Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
+        Status = AGESA_SUCCESS;
+        break;
+      case DeassertSlotReset:
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+        Data8 |= BIT6 ; 
+        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
+        Status = AGESA_SUCCESS;
+        break;
+      }
+      break;
+  case 6:
+      switch (ResetInfo->ResetControl)
+      {
+      case AssertSlotReset:
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+        Data8 &= ~(UINT8)BIT6 ;
+        Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
+        Status = AGESA_SUCCESS;
+        break;
+      case DeassertSlotReset:
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+        Data8 |= BIT6 ; 
+        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
+        Status = AGESA_SUCCESS;
+        break;
+      }
+      break;
+  case 7:
+      switch (ResetInfo->ResetControl)
+      {
+      case AssertSlotReset:
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+        Data8 &= ~(UINT8)BIT6 ;
+        Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
+        Status = AGESA_SUCCESS;
+        break;
+      case DeassertSlotReset:
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+        Data8 |= BIT6 ;
+        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
+        Status = AGESA_SUCCESS;
+        break;
+      }
+      break;
+  }
+  return  Status;
+}
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h
new file mode 100644
index 0000000000..2912ec6f51
--- /dev/null
+++ b/src/mainboard/amd/inagua/BiosCallOuts.h
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#define REQUIRED_CALLOUTS     12
+#define BIOS_HEAP_START_ADDRESS  0x00010000
+#define BIOS_HEAP_SIZE       0x20000   /* 64MB */
+
+typedef struct _BIOS_HEAP_MANAGER {
+  //UINT32 AvailableSize;
+  UINT32 StartOfAllocatedNodes;
+  UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+  UINT32 BufferHandle;
+  UINT32 BufferSize;
+  UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+/*
+ * CALLOUTS
+ */
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* REQUIRED CALLOUTS
+ * AGESA ADVANCED CALLOUTS - CPU
+ */  
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* AGESA ADVANCED CALLOUTS - MEMORY */
+AGESA_STATUS BiosReadSpd (UINT32  Func,UINT32  Data,VOID *ConfigPtr);
+
+/* BIOS DEFAULT RET */
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+#define SB_GPIO_REG02   2
+#define SB_GPIO_REG09   9
+#define SB_GPIO_REG10   10
+#define SB_GPIO_REG15   15
+#define SB_GPIO_REG17   17
+#define SB_GPIO_REG21   21
+#define SB_GPIO_REG25   25
+#define SB_GPIO_REG28   28
+#endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
new file mode 100644
index 0000000000..64f75631f6
--- /dev/null
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -0,0 +1,187 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+if BOARD_AMD_INAGUA
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+        def_bool y
+  select ARCH_X86
+        select DIMM_DDR3
+        select DIMM_UNREGISTERED
+  select CPU_AMD_AGESA_WRAPPER_FAMILY14
+  select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
+  select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
+  select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+  select SUPERIO_SMSC_KBC1100
+  select BOARD_HAS_FADT
+        select HAVE_BUS_CONFIG
+        select HAVE_OPTION_TABLE
+        select HAVE_PIRQ_TABLE
+        select HAVE_MP_TABLE
+        select HAVE_MAINBOARD_RESOURCES
+        select HAVE_HARD_RESET
+        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+        select LIFT_BSP_APIC_ID
+  select SERIAL_CPU_INIT
+  select AMDMCT
+        select HAVE_ACPI_TABLES
+  select BOARD_ROMSIZE_KB_2048
+  select ENABLE_APIC_EXT_ID
+  select TINY_BOOTBLOCK
+        select GFXUMA
+
+config AMD_AGESA
+        bool
+        default y
+
+config AMD_CIMX_SB800
+        bool
+        default y
+
+config MAINBOARD_DIR
+        string
+        default amd/inagua
+
+config APIC_ID_OFFSET
+        hex
+        default 0x0
+
+config MAINBOARD_PART_NUMBER
+        string
+        default "Inagua"
+
+config HW_MEM_HOLE_SIZEK
+        hex
+        default 0x200000
+
+config MAX_CPUS
+        int
+        default 2
+
+config MAX_PHYSICAL_CPUS
+        int
+        default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+        bool
+        default n
+
+config MEM_TRAIN_SEQ
+        int
+        default 2
+
+config SB_HT_CHAIN_ON_BUS0
+        int
+        default 1
+
+config HT_CHAIN_END_UNITID_BASE
+        hex
+        default 0x1
+
+config HT_CHAIN_UNITID_BASE
+        hex
+        default 0x0
+
+config IRQ_SLOT_COUNT
+        int
+        default 11
+
+config RAMTOP
+        hex
+        default 0x1000000
+
+config HEAP_SIZE
+        hex
+        default 0xc0000
+
+config STACK_SIZE
+        hex
+        default 0x10000
+
+config ACPI_SSDTX_NUM
+        int
+        default 0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+        hex
+        default 0x1510
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+        hex
+        default 0x1022
+
+config RAMBASE
+        hex
+        default 0x200000
+
+config SIO_PORT
+        hex
+        default 0x2e
+
+config DRIVERS_PS2_KEYBOARD
+	bool
+	default y
+
+config WARNINGS_ARE_ERRORS
+	bool
+	default n
+
+config PAYLOAD_ELF
+	bool
+	default y
+
+config FALLBACK_PAYLOAD_FILE
+	string "Payload path and filename"
+	depends on PAYLOAD_ELF
+	default "payloads/seabios/out/bios.bin.elf"
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config VGA_BIOS
+	bool
+	default y
+
+config FALLBACK_VGA_BIOS_FILE
+	string "VGA BIOS path and filename"
+	depends on VGA_BIOS
+	default "rom/video/OntarioGenericVBios.bin"
+
+config FALLBACK_VGA_BIOS_ID
+	string "VGA device PCI IDs"
+	depends on VGA_BIOS
+	default "1002,9802"
+
+config AHCI_ROM
+	bool
+	default y
+
+config AHCI_ROM_FILE
+	string "AHCI ROM path and filename"
+	depends on AHCI_ROM
+	default "rom/ahci/sb800.bin"
+
+config AHCI_ROM_ID
+	string "AHCI device PCI IDs"
+	depends on AHCI_ROM
+	default "1002,4391"
+
+endif # BOARD_AMD_INAGUA
+
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
new file mode 100644
index 0000000000..a8b8689e0b
--- /dev/null
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -0,0 +1,35 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += dimmSpd.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += dimmSpd.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
+
+ramstage-y += reset.c
+ramstage-y += pmio.c
+
+subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa
diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h
new file mode 100644
index 0000000000..eb756df9b3
--- /dev/null
+++ b/src/mainboard/amd/inagua/OptionsIds.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 12067 $   @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ *  This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ *    IDSOPT_IDS_ENABLED
+ *    IDSOPT_ERROR_TRAP_ENABLED
+ *    IDSOPT_CONTROL_ENABLED
+ *    IDSOPT_TRACING_ENABLED
+ *    IDSOPT_PERF_ANALYSIS
+ *    IDSOPT_ASSERT_ENABLED
+ *    IDS_DEBUG_PORT
+ *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED     TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+//#define IDSOPT_PERF_ANALYSIS   TRUE
+#define IDSOPT_ASSERT_ENABLED  TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED  FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW    FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT       FALSE
+//#define IDS_DEBUG_PORT    0x80
+
+#endif
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
new file mode 100644
index 0000000000..1840afc552
--- /dev/null
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
+
+PCIe_PORT_DESCRIPTOR PortList [] = {
+        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+        {
+          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+        },
+        // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+        {
+          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
+        },
+        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+        {
+          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+        },
+        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+        {
+          0,
+          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+        },
+        // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+        {
+          DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+        }       
+};
+
+PCIe_DDI_DESCRIPTOR DdiList [] = {
+        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+        {
+          0,   //Descriptor flags
+          PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+          //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+          {ConnectorTypeDP, Aux1, Hdp1}
+        },
+        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+        {
+          DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+          PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+          //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+          {ConnectorTypeDP, Aux2, Hdp2}
+        }
+};
+
+PCIe_COMPLEX_DESCRIPTOR Brazos = {
+        DESCRIPTOR_TERMINATE_LIST,
+        0,
+        &PortList[0],
+        &DdiList[0]
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  OemCustomizeInitEarly
+ *
+ *  Description:
+ *    This is the stub function will call the host environment through the binary block
+ *    interface (call-out port) to provide a user hook opportunity
+ *
+ *  Parameters:
+ *    @param[in]      **PeiServices
+ *    @param[in]      *InitEarly
+ *
+ *    @retval         VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+  IN  OUT AMD_EARLY_PARAMS    *InitEarly
+  )
+{
+  AGESA_STATUS         Status;
+  VOID                 *BrazosPcieComplexListPtr;
+  VOID                 *BrazosPciePortPtr;
+  VOID                 *BrazosPcieDdiPtr;
+
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  // GNB PCIe topology Porting
+
+  //
+  // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+  //
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  + 
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 + 
+                                         sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
+
+  AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+  if ( Status!= AGESA_SUCCESS) {
+    // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+    ASSERT(FALSE); 
+    return Status;
+  }
+  
+  BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+  AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+  BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+  AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
+  BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+ 
+  LibAmdMemFill (BrazosPcieComplexListPtr,
+                   0,
+                   sizeof (PCIe_COMPLEX_DESCRIPTOR),
+                   &InitEarly->StdHeader);
+
+  LibAmdMemFill (BrazosPciePortPtr,
+                   0,
+                   sizeof (PCIe_PORT_DESCRIPTOR) * 5,
+                   &InitEarly->StdHeader);
+     
+  LibAmdMemFill (BrazosPcieDdiPtr,
+                   0,
+                   sizeof (PCIe_DDI_DESCRIPTOR) * 2,
+                   &InitEarly->StdHeader);
+
+  LibAmdMemCopy  (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+  LibAmdMemCopy  (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
+  LibAmdMemCopy  (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
+
+
+  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
+  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+
+  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; 
+  InitEarly->GnbConfig.PsppPolicy      = 0; 
+}
+
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000000..f35d8db723
--- /dev/null
+++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+//GNB GPP Port4
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port5
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port6
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port7
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port8
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+VOID
+OemCustomizeInitEarly (
+  IN  OUT AMD_EARLY_PARAMS    *InitEarly
+  );
+  
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/inagua/acpi/cpstate.asl b/src/mainboard/amd/inagua/acpi/cpstate.asl
new file mode 100644
index 0000000000..5eca9cc5c7
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}
diff --git a/src/mainboard/amd/inagua/acpi/ide.asl b/src/mainboard/amd/inagua/acpi/ide.asl
new file mode 100644
index 0000000000..c79c18c07b
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}
diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl
new file mode 100644
index 0000000000..cb5039425f
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/routing.asl
@@ -0,0 +1,398 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+
+		Package(){0x0009FFFF, 0, INTB, 0 },
+		Package(){0x0009FFFF, 1, INTC, 0 },
+		Package(){0x0009FFFF, 2, INTD, 0 },
+		Package(){0x0009FFFF, 3, INTA, 0 },
+
+		Package(){0x000AFFFF, 0, INTC, 0 },
+		Package(){0x000AFFFF, 1, INTD, 0 },
+		Package(){0x000AFFFF, 2, INTA, 0 },
+		Package(){0x000AFFFF, 3, INTB, 0 },
+
+		Package(){0x000BFFFF, 0, INTD, 0 },
+		Package(){0x000BFFFF, 1, INTA, 0 },
+		Package(){0x000BFFFF, 2, INTB, 0 },
+		Package(){0x000BFFFF, 3, INTC, 0 },
+
+		Package(){0x000CFFFF, 0, INTA, 0 },
+		Package(){0x000CFFFF, 1, INTB, 0 },
+		Package(){0x000CFFFF, 2, INTC, 0 },
+		Package(){0x000CFFFF, 3, INTD, 0 },
+
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+
+		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, 0, 18 },
+		package(){0x0001FFFF, 1, 0, 19 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, 0, 17 }, */
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Package(){0x0006FFFF, 0, 0, 18 }, */
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Package(){0x0007FFFF, 0, 0, 19 }, */
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Dev 9 - PCIe Bridge for network card */
+		Package(){0x0009FFFF, 0, 0, 17 },
+		/* Package(){0x0009FFFF, 1, 0, 16 }, */
+		/* Package(){0x0009FFFF, 2, 0, 17 }, */
+		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		/* Bus 0, Dev A - PCIe Bridge for network card */
+		Package(){0x000AFFFF, 0, 0, 18 },
+		/* Package(){0x000AFFFF, 1, 0, 16 }, */
+		/* Package(){0x000AFFFF, 2, 0, 17 }, */
+		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+		 * EHCI, dev 18, 19 func 2 */
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		/* Package(){0x0012FFFF, 2, 0, 18 }, */
+
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		/* Package(){0x0013FFFF, 2, 0, 16 }, */
+
+		/* Package(){0x00140000, 0, 0, 16 }, */
+
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+
+		/* TODO: pcie */
+		Package(){0x0015FFFF, 0, 0, 16 },
+		Package(){0x0015FFFF, 1, 0, 17 },
+		Package(){0x0015FFFF, 2, 0, 18 },
+		Package(){0x0015FFFF, 3, 0, 19 },
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+	Name(APR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE0, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APE0, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PE1, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APE1, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PE2, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APE2, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE3, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APE3, Package(){
+		/* PCIe slot - Hooked to PCIe */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}
diff --git a/src/mainboard/amd/inagua/acpi/sata.asl b/src/mainboard/amd/inagua/acpi/sata.asl
new file mode 100644
index 0000000000..bd4acf0110
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/amd/inagua/acpi/ssdt2.asl b/src/mainboard/amd/inagua/acpi/ssdt2.asl
new file mode 100644
index 0000000000..ef1a4bf9eb
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/ssdt2.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+	Scope (_SB)
+	{
+		External (DADD, MethodObj)
+		External (GHCE, MethodObj)
+		External (GHCN, MethodObj)
+		External (GHCL, MethodObj)
+		External (GHCD, MethodObj)
+		External (GNUS, MethodObj)
+		External (GIOR, MethodObj)
+		External (GMEM, MethodObj)
+		External (GWBN, MethodObj)
+		External (GBUS, MethodObj)
+
+		External (PICF)
+
+		External (\_SB.PCI0.LNKA, DeviceObj)
+		External (\_SB.PCI0.LNKB, DeviceObj)
+		External (\_SB.PCI0.LNKC, DeviceObj)
+		External (\_SB.PCI0.LNKD, DeviceObj)
+
+		Device (PCIX)
+		{
+
+		// BUS ? Second HT Chain
+		Name (HCIN, 0xcc)  // HC2 0x01
+
+		Name (_UID,	 0xdd)	// HC 0x03
+
+		Name (_HID, "PNP0A03")
+
+		Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+		{
+			Return (DADD(GHCN(HCIN), 0x00000000))
+		}
+
+		Method (_BBN, 0, NotSerialized)
+		{
+			 Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+		}
+
+		Method (_STA, 0, NotSerialized)
+		{
+			Return (\_SB.GHCE(HCIN))
+		}
+
+		Method (_CRS, 0, NotSerialized)
+		{
+			Name (BUF0, ResourceTemplate () { })
+			Store( GHCN(HCIN), Local4)
+			Store( GHCL(HCIN), Local5)
+
+			Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+			Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+			Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+			Return (Local3)
+		}
+
+			#include "acpi/pci2_hc.asl"
+		}
+	}
+
+}
+
diff --git a/src/mainboard/amd/inagua/acpi/ssdt3.asl b/src/mainboard/amd/inagua/acpi/ssdt3.asl
new file mode 100644
index 0000000000..68a4b95abe
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/ssdt3.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+	Scope (_SB)
+	{
+		External (DADD, MethodObj)
+		External (GHCE, MethodObj)
+		External (GHCN, MethodObj)
+		External (GHCL, MethodObj)
+		External (GHCD, MethodObj)
+		External (GNUS, MethodObj)
+		External (GIOR, MethodObj)
+		External (GMEM, MethodObj)
+		External (GWBN, MethodObj)
+		External (GBUS, MethodObj)
+
+		External (PICF)
+
+		External (\_SB.PCI0.LNKA, DeviceObj)
+		External (\_SB.PCI0.LNKB, DeviceObj)
+		External (\_SB.PCI0.LNKC, DeviceObj)
+		External (\_SB.PCI0.LNKD, DeviceObj)
+
+		Device (PCIX)
+		{
+
+			// BUS ? Second HT Chain
+			Name (HCIN, 0xcc)  // HC2 0x01
+
+			Name (_UID,	 0xdd)	// HC 0x03
+
+			Name (_HID, "PNP0A03")
+
+			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+			{
+				Return (DADD(GHCN(HCIN), 0x00000000))
+			}
+
+			Method (_BBN, 0, NotSerialized)
+			{
+				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+			}
+
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (\_SB.GHCE(HCIN))
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate () { })
+				Store( GHCN(HCIN), Local4)
+				Store( GHCL(HCIN), Local5)
+
+				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+				Return (Local3)
+			}
+
+			#include "acpi/pci3_hc.asl"
+		}
+	}
+
+}
+
diff --git a/src/mainboard/amd/inagua/acpi/ssdt4.asl b/src/mainboard/amd/inagua/acpi/ssdt4.asl
new file mode 100644
index 0000000000..e06fe8ab85
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/ssdt4.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+	Scope (_SB)
+	{
+		External (DADD, MethodObj)
+		External (GHCE, MethodObj)
+		External (GHCN, MethodObj)
+		External (GHCL, MethodObj)
+		External (GHCD, MethodObj)
+		External (GNUS, MethodObj)
+		External (GIOR, MethodObj)
+		External (GMEM, MethodObj)
+		External (GWBN, MethodObj)
+		External (GBUS, MethodObj)
+
+		External (PICF)
+
+		External (\_SB.PCI0.LNKA, DeviceObj)
+		External (\_SB.PCI0.LNKB, DeviceObj)
+		External (\_SB.PCI0.LNKC, DeviceObj)
+		External (\_SB.PCI0.LNKD, DeviceObj)
+
+		Device (PCIX)
+		{
+
+			// BUS ? Second HT Chain
+			Name (HCIN, 0xcc)  // HC2 0x01
+
+			Name (_UID,	 0xdd)	// HC 0x03
+
+			Name (_HID, "PNP0A03")
+
+			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+			{
+				Return (DADD(GHCN(HCIN), 0x00000000))
+			}
+
+			Method (_BBN, 0, NotSerialized)
+			{
+				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+			}
+
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (\_SB.GHCE(HCIN))
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate () { })
+				Store( GHCN(HCIN), Local4)
+				Store( GHCL(HCIN), Local5)
+
+				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+				Return (Local3)
+			}
+
+			#include "acpi/pci4_hc.asl"
+		}
+	}
+
+}
+
diff --git a/src/mainboard/amd/inagua/acpi/ssdt5.asl b/src/mainboard/amd/inagua/acpi/ssdt5.asl
new file mode 100644
index 0000000000..a141a378d2
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/ssdt5.asl
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+	Scope (_SB)
+	{
+	External (DADD, MethodObj)
+	External (GHCE, MethodObj)
+	External (GHCN, MethodObj)
+	External (GHCL, MethodObj)
+	External (GHCD, MethodObj)
+	External (GNUS, MethodObj)
+	External (GIOR, MethodObj)
+	External (GMEM, MethodObj)
+	External (GWBN, MethodObj)
+	External (GBUS, MethodObj)
+
+	External (PICF)
+
+	External (\_SB.PCI0.LNKA, DeviceObj)
+	External (\_SB.PCI0.LNKB, DeviceObj)
+	External (\_SB.PCI0.LNKC, DeviceObj)
+	External (\_SB.PCI0.LNKD, DeviceObj)
+
+		Device (PCIX)
+		{
+
+			// BUS ? Second HT Chain
+			Name (HCIN, 0xcc)  // HC2 0x01
+
+			Name (_UID,	 0xdd)	// HC 0x03
+
+			Name (_HID, "PNP0A03")
+
+			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+			{
+				Return (DADD(GHCN(HCIN), 0x00000000))
+			}
+
+			Method (_BBN, 0, NotSerialized)
+			{
+				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+			}
+
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (\_SB.GHCE(HCIN))
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate () { })
+				Store( GHCN(HCIN), Local4)
+				Store( GHCL(HCIN), Local5)
+
+				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+				Return (Local3)
+			}
+
+			#include "acpi/pci5_hc.asl"
+		}
+	}
+
+}
+
diff --git a/src/mainboard/amd/inagua/acpi/usb.asl b/src/mainboard/amd/inagua/acpi/usb.asl
new file mode 100644
index 0000000000..181d685491
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi/usb.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "usb.asl"
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+    	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ 	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
new file mode 100644
index 0000000000..da08a79a05
--- /dev/null
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -0,0 +1,252 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+
+#include "agesawrapper.h"
+
+#define DUMP_ACPI_TABLES 0
+extern u32 apicid_sb800;
+
+
+#if DUMP_ACPI_TABLES == 1
+
+static void dump_mem(u32 start, u32 end)
+{
+
+  u32 i;
+  print_debug("dump_mem:");
+  for (i = start; i < end; i++) {
+    if ((i & 0xf) == 0) {
+      printk(BIOS_DEBUG, "\n%08x:", i);
+    }
+    printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+  }
+  print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+  /* Just a dummy */
+  return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+  
+  /* create all subtables for processors */
+  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
+  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
+  
+  /* Write SB800 IOAPIC, only one */
+  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
+             IO_APIC_ADDR, 0);
+
+  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+            current, 0, 0, 2, 0);
+  
+  /* 0: mean bus 0--->ISA */
+  /* 0: PIC 0 */
+  /* 2: APIC 2 */
+  /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+  /* create all subtables for processors */
+  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+  /* 1: LINT1 connect to NMI */
+
+  return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+  // Not implemented
+  return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+  /* No NUMA, no SRAT */
+  return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+  unsigned long current;
+  acpi_rsdp_t *rsdp;
+  acpi_rsdt_t *rsdt;
+  acpi_hpet_t *hpet;
+  acpi_madt_t *madt;
+  acpi_srat_t *srat;
+  acpi_slit_t *slit;
+  acpi_fadt_t *fadt;
+  acpi_facs_t *facs;
+  acpi_header_t *dsdt;
+  acpi_header_t *ssdt;
+
+  get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+  /* Align ACPI tables to 16 bytes */
+  start = (start + 0x0f) & -0x10;
+  current = start;
+
+  printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+  /* We need at least an RSDP and an RSDT Table */
+  rsdp = (acpi_rsdp_t *) current;
+  current += sizeof(acpi_rsdp_t);
+  rsdt = (acpi_rsdt_t *) current;
+  current += sizeof(acpi_rsdt_t);
+
+  /* clear all table memory */
+  memset((void *)start, 0, current - start);
+
+  acpi_write_rsdp(rsdp, rsdt, NULL);
+  acpi_write_rsdt(rsdt);
+
+  /*
+   * We explicitly add these tables later on:
+   */
+#if 0 // Don't need HPET table.
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+  hpet = (acpi_hpet_t *) current;
+  current += sizeof(acpi_hpet_t);
+  acpi_create_hpet(hpet);
+  acpi_add_table(rsdp, hpet);
+#endif
+
+  /* If we want to use HPET Timers Linux wants an MADT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+  madt = (acpi_madt_t *) current;
+  acpi_create_madt(madt);
+  current += madt->header.length;
+  acpi_add_table(rsdp, madt);
+
+  /* SRAT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+  srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+  if (srat != NULL) {
+    memcpy(current, srat, srat->header.length);
+    srat = (acpi_srat_t *) current;
+    //acpi_create_srat(srat);
+    current += srat->header.length;
+    acpi_add_table(rsdp, srat);
+  }
+
+  /* SLIT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+  slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+  if (slit != NULL) {
+    memcpy(current, slit, slit->header.length);
+    slit = (acpi_slit_t *) current;
+    //acpi_create_slit(slit);
+    current += slit->header.length;
+    acpi_add_table(rsdp, slit);
+  }
+
+  /* SSDT */
+  current   = ( current + 0x0f) & -0x10;
+  printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+  ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+  if (ssdt != NULL) {
+    memcpy(current, ssdt, ssdt->length);
+    ssdt = (acpi_header_t *) current;
+    current += ssdt->length;
+  }
+  else {
+    ssdt = (acpi_header_t *) current;
+    memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+    current += ssdt->length;
+    memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+   /* recalculate checksum */
+    ssdt->checksum = 0;
+    ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+  }
+  acpi_add_table(rsdp,ssdt);
+
+  printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+
+  /* DSDT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+  dsdt = (acpi_header_t *)current; // it will used by fadt
+  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+  current += dsdt->length;
+  memcpy(dsdt, &AmlCode, dsdt->length);
+  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+  /* FACS */ // it needs 64 bit alignment
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+  facs = (acpi_facs_t *) current; // it will be used by fadt
+  current += sizeof(acpi_facs_t);
+  acpi_create_facs(facs);
+
+  /* FADT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+  fadt = (acpi_fadt_t *) current;
+  current += sizeof(acpi_fadt_t);
+
+  acpi_create_fadt(fadt, facs, dsdt);
+  acpi_add_table(rsdp, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+  printk(BIOS_DEBUG, "rsdp\n");
+  dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+  printk(BIOS_DEBUG, "rsdt\n");
+  dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+  printk(BIOS_DEBUG, "madt\n");
+  dump_mem(madt, ((void *)madt) + madt->header.length);
+
+  printk(BIOS_DEBUG, "srat\n");
+  dump_mem(srat, ((void *)srat) + srat->header.length);
+
+  printk(BIOS_DEBUG, "slit\n");
+  dump_mem(slit, ((void *)slit) + slit->header.length);
+
+  printk(BIOS_DEBUG, "ssdt\n");
+  dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+  printk(BIOS_DEBUG, "fadt\n");
+  dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+  printk(BIOS_INFO, "ACPI: done.\n");
+  return current;
+}
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
new file mode 100644
index 0000000000..7944a58179
--- /dev/null
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -0,0 +1,541 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+ 
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable    = NULL;
+VOID *AcpiPstate  = NULL;
+VOID *AcpiSrat    = NULL;
+VOID *AcpiSlit    = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib    = NULL; 
+ 
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ 
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ 
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+UINT32 
+agesawrapper_amdinitcpuio (
+  VOID
+  )
+{
+  AGESA_STATUS                  Status;
+  UINT64                        MsrReg;
+  UINT32                        PciData;
+  PCI_ADDR                      PciAddress;
+  AMD_CONFIG_PARAMS             StdHeader;
+  
+  /* Enable MMIO on AMD CPU Address Map Controller */
+  
+  /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+  PciData = 0x00000B00;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+  PciData = 0x00000A03;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  
+  /* Set TOM-DFFFFFFF to Node0 Link0. */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+  PciData = 0x00DFFF00;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+  MsrReg = (MsrReg >> 8) | 3;
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+  PciData = (UINT32)MsrReg;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
+  PciData = 0x00FFFF00 | 0x80;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
+  PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+  PciData = 0x0000F000;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+  PciData = 0x00000013;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  Status = AGESA_SUCCESS;
+  return (UINT32)Status;
+}
+ 
+UINT32 
+agesawrapper_amdinitmmio (
+  VOID
+  )
+{
+  AGESA_STATUS                  Status;
+  UINT64                        MsrReg;
+  UINT32                        PciData;
+  PCI_ADDR                      PciAddress;
+  AMD_CONFIG_PARAMS             StdHeader;
+  
+  /*
+   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+   Address MSR register.
+  */
+  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+  LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+  
+  /*
+   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+  */
+  LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+  MsrReg = MsrReg | 0x0000400000000000;
+  LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+  
+  /* Set Ontario Link Data */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+  PciData = 0x01308002;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+  PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
+  
+
+  /* Set ROM cache onto WP to decrease post time */
+  MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
+  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+  MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+  Status = AGESA_SUCCESS;
+  return (UINT32)Status;
+}
+
+UINT32 
+agesawrapper_amdinitreset (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  AMD_INTERFACE_PARAMS AmdParamStruct;
+  AMD_RESET_PARAMS AmdResetParams;
+  
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+
+  LibAmdMemFill (&AmdResetParams,
+                 0,
+                 sizeof (AMD_RESET_PARAMS),
+                 &(AmdResetParams.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+  AmdParamStruct.AllocationMethod = ByHost;
+  AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+  AmdParamStruct.NewStructPtr = &AmdResetParams;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = NULL;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+  AmdCreateStruct (&AmdParamStruct);
+  AmdResetParams.HtConfig.Depth = 0;
+  
+  status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+  return (UINT32)status;
+ }  
+  
+UINT32 
+agesawrapper_amdinitearly (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  AMD_INTERFACE_PARAMS AmdParamStruct;
+  AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
+  
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+  AmdParamStruct.AllocationMethod = PreMemHeap;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+  AmdCreateStruct (&AmdParamStruct);
+  
+  AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+  OemCustomizeInitEarly (AmdEarlyParamsPtr);
+  
+  status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+
+  return (UINT32)status;
+}
+
+UINT32 
+agesawrapper_amdinitpost (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  UINT16                  i;
+  UINT32          *HeadPtr;
+  AMD_INTERFACE_PARAMS  AmdParamStruct;
+  BIOS_HEAP_MANAGER    *BiosManagerPtr;
+
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+  AmdParamStruct.AllocationMethod = PreMemHeap;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+  AmdCreateStruct (&AmdParamStruct);
+  status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+  /* Initialize heap space */
+  BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+  HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+  for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+  {
+    *HeadPtr = 0x00000000;
+    HeadPtr++;
+  }
+  BiosManagerPtr->StartOfAllocatedNodes = 0;
+  BiosManagerPtr->StartOfFreedNodes = 0;
+
+  return (UINT32)status;
+}
+
+UINT32 
+agesawrapper_amdinitenv (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  AMD_INTERFACE_PARAMS AmdParamStruct;
+  PCI_ADDR             PciAddress;
+  UINT32               PciValue;
+
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+  AmdParamStruct.AllocationMethod = PostMemDram;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+  AmdCreateStruct (&AmdParamStruct);
+  status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  /* Initialize Subordinate Bus Number and Secondary Bus Number
+   * In platform BIOS this address is allocated by PCI enumeration code
+     Modify D1F0x18
+   */  
+  PciAddress.Address.Bus = 0;
+  PciAddress.Address.Device = 1;
+  PciAddress.Address.Function = 0;
+  PciAddress.Address.Register = 0x18;
+  /* Write to D1F0x18 */
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+  PciValue |= 0x00010100;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+  /* Initialize GMM Base Address for Legacy Bridge Mode
+  *  Modify B1D5F0x18
+  */
+  PciAddress.Address.Bus = 1;
+  PciAddress.Address.Device = 5;
+  PciAddress.Address.Function = 0;
+  PciAddress.Address.Register = 0x18;
+
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+  PciValue |= 0x96000000;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+  /* Initialize FB Base Address for Legacy Bridge Mode
+  * Modify B1D5F0x10
+  */
+  PciAddress.Address.Register = 0x10;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+  PciValue |= 0x80000000;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+  /* Initialize GMM Base Address for Pcie Mode
+  *  Modify B0D1F0x18
+  */
+  PciAddress.Address.Bus = 0;
+  PciAddress.Address.Device = 1;
+  PciAddress.Address.Function = 0;
+  PciAddress.Address.Register = 0x18;
+
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+  PciValue |= 0x96000000;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+  /* Initialize FB Base Address for Pcie Mode
+  *  Modify B0D1F0x10
+  */
+  PciAddress.Address.Register = 0x10;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+  PciValue |= 0x80000000;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+
+  /* Initialize MMIO Base and Limit Address
+  *  Modify B0D1F0x20
+  */
+  PciAddress.Address.Bus = 0;
+  PciAddress.Address.Device = 1;
+  PciAddress.Address.Function = 0;
+  PciAddress.Address.Register = 0x20;
+
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+  PciValue |= 0x96009600;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+  /* Initialize MMIO Prefetchable Memory Limit and Base
+  *  Modify B0D1F0x24
+  */
+  PciAddress.Address.Register = 0x24;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+  PciValue |= 0x8FF18001;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+  AmdReleaseStruct (&AmdParamStruct);
+
+  return (UINT32)status;
+}
+
+VOID *
+agesawrapper_getlateinitptr (
+  int pick
+  )
+{
+  switch (pick) {
+    case PICK_DMI:
+      return DmiTable;
+
+    case PICK_PSTATE:
+      return AcpiPstate;
+
+    case PICK_SRAT:
+      return AcpiSrat;
+
+    case PICK_SLIT:
+      return AcpiSlit;
+    case PICK_WHEA_MCE:
+      return AcpiWheaMce;
+    case PICK_WHEA_CMC:
+      return AcpiWheaCmc;
+    case PICK_ALIB:
+      return AcpiAlib;
+    defaut:
+      return NULL;
+  }
+}
+
+UINT32 
+agesawrapper_amdinitmid (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  AMD_INTERFACE_PARAMS AmdParamStruct;
+  
+  /* Enable MMIO on AMD CPU Address Map Controller */
+  agesawrapper_amdinitcpuio ();
+  
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+  AmdParamStruct.AllocationMethod = PostMemDram;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+  AmdCreateStruct (&AmdParamStruct);
+
+  status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+
+  return (UINT32)status;
+}
+
+UINT32 
+agesawrapper_amdinitlate (
+  VOID
+  )
+{
+  AGESA_STATUS Status;
+  AMD_LATE_PARAMS AmdLateParams;
+
+  LibAmdMemFill (&AmdLateParams,
+                 0,
+                 sizeof (AMD_LATE_PARAMS),
+                 &(AmdLateParams.StdHeader));
+
+  AmdLateParams.StdHeader.AltImageBasePtr = 0;
+  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdLateParams.StdHeader.Func = 0;
+  AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+  Status = AmdInitLate (&AmdLateParams);
+  if (Status != AGESA_SUCCESS) {
+    agesawrapper_amdreadeventlog();
+    ASSERT(Status == AGESA_SUCCESS);
+  }
+
+  DmiTable       = AmdLateParams.DmiTable;
+  AcpiPstate     = AmdLateParams.AcpiPState;
+  AcpiSrat       = AmdLateParams.AcpiSrat;
+  AcpiSlit       = AmdLateParams.AcpiSlit;
+
+  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
+  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
+  AcpiAlib       = AmdLateParams.AcpiAlib;
+
+  return (UINT32)Status;
+}
+
+UINT32 
+agesawrapper_amdlaterunaptask (
+  UINT32 Data, 
+  VOID *ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+  AMD_LATE_PARAMS AmdLateParams;
+
+  LibAmdMemFill (&AmdLateParams,
+                 0,
+                 sizeof (AMD_LATE_PARAMS),
+                 &(AmdLateParams.StdHeader));
+
+  AmdLateParams.StdHeader.AltImageBasePtr = 0;
+  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdLateParams.StdHeader.Func = 0;
+  AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+  Status = AmdLateRunApTask (&AmdLateParams);
+  if (Status != AGESA_SUCCESS) {
+    agesawrapper_amdreadeventlog();
+    ASSERT(Status == AGESA_SUCCESS);
+  }
+
+  DmiTable       = AmdLateParams.DmiTable;
+  AcpiPstate     = AmdLateParams.AcpiPState;
+  AcpiSrat       = AmdLateParams.AcpiSrat;
+  AcpiSlit       = AmdLateParams.AcpiSlit;
+
+  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
+  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
+  AcpiAlib       = AmdLateParams.AcpiAlib;
+
+  return (UINT32)Status;
+}
+
+UINT32 
+agesawrapper_amdreadeventlog (
+  VOID
+  )
+{
+  AGESA_STATUS Status;
+  EVENT_PARAMS AmdEventParams;
+
+  LibAmdMemFill (&AmdEventParams,
+                 0,
+                 sizeof (EVENT_PARAMS),
+                 &(AmdEventParams.StdHeader));
+
+  AmdEventParams.StdHeader.AltImageBasePtr = 0;
+  AmdEventParams.StdHeader.CalloutPtr = NULL;
+  AmdEventParams.StdHeader.Func = 0;
+  AmdEventParams.StdHeader.ImageBasePtr = 0;
+  Status = AmdReadEventLog (&AmdEventParams);
+  while (AmdEventParams.EventClass != 0) {
+    printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+    printk(BIOS_DEBUG,"  Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+    printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+    Status = AmdReadEventLog (&AmdEventParams);
+  }
+
+  return (UINT32)Status;
+}
diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h
new file mode 100644
index 0000000000..fd46dc6358
--- /dev/null
+++ b/src/mainboard/amd/inagua/agesawrapper.h
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+ 
+  
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID    0x1022
+#define AMD_APU_SSID    0x1234
+#define PCIE_BASE_ADDRESS   CONFIG_MMCONF_BASE_ADDRESS
+
+
+enum {
+  PICK_DMI,       /* DMI Interface */
+  PICK_PSTATE,    /* Acpi Pstate SSDT Table */
+  PICK_SRAT,      /* SRAT Table */
+  PICK_SLIT,      /* SLIT Table */
+  PICK_WHEA_MCE,  /* WHEA MCE table */
+  PICK_WHEA_CMC,  /* WHEA CMV table */
+  PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
+};
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  UINT32 CalloutName;
+  AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ 
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ 
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+ 
+//void brazos_platform_stage(void);
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+UINT32 agesawrapper_amdreadeventlog (void);
+UINT32 agesawrapper_amdinitmmio (void);
+void *agesawrapper_getlateinitptr (int pick);
+
+#endif
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
new file mode 100644
index 0000000000..686f7fa717
--- /dev/null
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -0,0 +1,434 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 23714 $   @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
+ */
+
+#include "AGESA.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+
+/*  Select the cpu family.  */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT TRUE
+#define INSTALL_FAMILY_15_SUPPORT FALSE
+
+/*  Select the cpu socket type.  */
+#define INSTALL_G34_SOCKET_SUPPORT  FALSE
+#define INSTALL_C32_SOCKET_SUPPORT  FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FP1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT  TRUE
+#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+
+/* 
+ * Agesa optional capabilities selection.  
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE    
+#define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
+#define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
+#define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE
+
+#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT      TRUE
+#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT      TRUE
+#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT      TRUE
+#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT      TRUE
+#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT      TRUE
+#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT      FALSE
+#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT      TRUE
+#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
+
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
+//#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
+#define BLDOPT_REMOVE_DQS_TRAINING            FALSE
+//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
+//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
+  #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
+  #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
+  #define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
+  #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
+  #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
+  #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
+//#define BLDOPT_REMOVE_SRAT            TRUE
+//#define BLDOPT_REMOVE_SLIT            TRUE
+//#define BLDOPT_REMOVE_WHEA            TRUE
+//#define BLDOPT_REMOVE_DMI             TRUE
+//#define BLDOPT_REMOVE_HT_ASSIST         TRUE
+//#define BLDOPT_REMOVE_ATM_MODE          TRUE
+//#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE  
+#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
+//#define BLDOPT_REMOVE_C6_STATE          TRUE
+//#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
+#define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
+
+/*
+ * Agesa entry points used in this implementation.
+ */
+#define AGESA_ENTRY_INIT_RESET                    TRUE
+#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
+#define AGESA_ENTRY_INIT_EARLY                    TRUE
+#define AGESA_ENTRY_INIT_POST                     TRUE
+#define AGESA_ENTRY_INIT_ENV                      TRUE
+#define AGESA_ENTRY_INIT_MID                      TRUE
+#define AGESA_ENTRY_INIT_LATE                     TRUE
+#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+#define AGESA_ENTRY_INIT_RESUME                   TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/* 
+ * Agesa configuration values selection.  
+ * Uncomment and specify the value for the configuration options
+ * needed by the system. 
+ */
+
+/* The fixed MTRR values to be set after memory initialization. */
+CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
+{
+  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
+  { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
+
+#define BLDCFG_VRM_CURRENT_LIMIT                24000
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT             0
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD          24000
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD       1
+#define BLDCFG_VRM_SLEW_RATE                    5000
+//#define BLDCFG_VRM_NB_SLEW_RATE                 5000
+//#define BLDCFG_VRM_ADDITIONAL_DELAY             0
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY          0
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE            TRUE
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE         FALSE
+#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT         6000
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT      0
+
+//#define BLDCFG_PROCESSOR_SCOPE_NAME0            'C'
+//#define BLDCFG_PROCESSOR_SCOPE_NAME1            '0'
+//#define BLDCFG_PROCESSOR_SCOPE_IN_SB            FALSE
+#define BLDCFG_PLAT_NUM_IO_APICS                3
+//#define BLDCFG_PLATFORM_C1E_MODE                C1eModeDisabled
+//#define BLDCFG_PLATFORM_C1E_OPDATA              0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
+#define BLDCFG_PLATFORM_CSTATE_MODE             CStateModeC6
+#define BLDCFG_PLATFORM_CSTATE_OPDATA           0x840
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
+//#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
+#define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
+#define BLDCFG_AP_MTRR_SETTINGS_LIST            &OntarioApMtrrSettingsList
+#define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
+//#define BLDCFG_STARTING_BUSNUM                  0
+//#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
+//#define BLDCFG_ALLOCATED_BUSNUMS                0x20
+//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST         0
+//#define BLDCFG_BUID_SWAP_LIST                   0
+//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST  0
+//#define BLDCFG_HTFABRIC_LIMITS_LIST             0
+//#define BLDCFG_HTCHAIN_LIMITS_LIST              0
+//#define BLDCFG_BUS_NUMBERS_LIST                 0
+//#define BLDCFG_IGNORE_LINK_LIST                 0
+//#define BLDCFG_LINK_SKIP_REGANG_LIST            0
+//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST       0
+//#define BLDCFG_USE_HT_ASSIST                    TRUE
+//#define BLDCFG_USE_ATM_MODE                     TRUE
+//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE       Nfcm
+#define BLDCFG_S3_LATE_RESTORE                    FALSE
+//#define BLDCFG_USE_32_BYTE_REFRESH              FALSE
+//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY   FALSE
+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE       Performance
+//#define BLDCFG_SET_HTCRC_SYNC_FLOOD             FALSE
+//#define BLDCFG_USE_UNIT_ID_CLUMPING             FALSE
+//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP       0
+//#define BLDCFG_CFG_GNB_HD_AUDIO                 TRUE
+//#define BLDCFG_CFG_ABM_SUPPORT                  FALSE
+//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE         0
+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL       0
+//#define BLDCFG_MEM_INIT_PSTATE                  0
+//#define BLDCFG_AMD_PSTATE_CAP_VALUE             0
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT       DDR1333_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED             TRUE
+//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE         TRUE
+//#define BLDCFG_MEMORY_QUADRANK_TYPE             QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_SODIMM_CAPABLE            TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE            FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING  TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING  FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING      FALSE
+#define BLDCFG_MEMORY_POWER_DOWN                TRUE
+#define BLDCFG_POWER_DOWN_MODE                  POWER_DOWN_BY_CHIP_SELECT
+//#define BLDCFG_ONLINE_SPARE                     FALSE
+//#define BLDCFG_MEMORY_PARITY_ENABLE             FALSE
+#define BLDCFG_BANK_SWIZZLE                     TRUE
+#define BLDCFG_TIMING_MODE_SELECT               TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT              DDR1333_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL             TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM              FALSE
+#define BLDCFG_USE_BURST_MODE                   FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON             FALSE
+//#define BLDCFG_ENABLE_ECC_FEATURE               TRUE
+//#define BLDCFG_ECC_REDIRECTION                  FALSE
+//#define BLDCFG_SCRUB_DRAM_RATE                  0
+//#define BLDCFG_SCRUB_L2_RATE                    0
+//#define BLDCFG_SCRUB_L3_RATE                    0
+//#define BLDCFG_SCRUB_IC_RATE                    0
+//#define BLDCFG_SCRUB_DC_RATE                    0
+//#define BLDCFG_ECC_SYNC_FLOOD                   0
+//#define BLDCFG_ECC_SYMBOL_SIZE                  0
+//#define BLDCFG_1GB_ALIGN                        FALSE
+#define BLDCFG_UMA_ALLOCATION_MODE              UMA_AUTO
+#define BLDCFG_UMA_ALLOCATION_SIZE              0
+#define BLDCFG_UMA_ABOVE4G_SUPPORT              FALSE
+#define BLDCFG_UMA_ALIGNMENT                    NO_UMA_ALIGNED
+#define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
+#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
+
+/*  Include the files that instantiate the configuration definitions.  */
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "BrazosPI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ *                        CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *  use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+  //
+  // The following macros are supported (use comma to separate macros):
+  //
+  // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+  //      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+  //      AGESA will base on this value to disable unused MemClk to save power.
+  //      Example:
+  //      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+  //           Bit AM3/S1g3 pin name
+  //           0   M[B,A]_CLK_H/L[0]
+  //           1   M[B,A]_CLK_H/L[1]
+  //           2   M[B,A]_CLK_H/L[2]
+  //           3   M[B,A]_CLK_H/L[3]
+  //           4   M[B,A]_CLK_H/L[4]
+  //           5   M[B,A]_CLK_H/L[5]
+  //           6   M[B,A]_CLK_H/L[6]
+  //           7   M[B,A]_CLK_H/L[7]
+  //      And platform has the following routing:
+  //           CS0   M[B,A]_CLK_H/L[4]
+  //           CS1   M[B,A]_CLK_H/L[2]
+  //           CS2   M[B,A]_CLK_H/L[3]
+  //           CS3   M[B,A]_CLK_H/L[5]
+  //      Then platform can specify the following macro:
+  //      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+  //
+  // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+  //      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+  //      AGESA will base on this value to tristate unused CKE to save power.
+  //
+  // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+  //      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+  //      AGESA will base on this value to tristate unused ODT pins to save power.
+  //
+  // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+  //      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+  //      AGESA will base on this value to tristate unused Chip select to save power.
+  //
+  // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+  //      Specifies the number of DIMM slots per channel.
+  //
+  // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+  //      Specifies the number of Chip selects per channel.
+  //
+  // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+  //      Specifies the number of channels per socket.
+  //
+  // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+  //      Specifies DDR bus speed of channel ChannelID on socket SocketID.
+  //
+  // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+  //      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+  //
+  // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+  //      Byte6Seed, Byte7Seed, ByteEccSeed)
+  //      Specifies the write leveling seed for a channel of a socket.
+  //
+  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+  NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+  PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+#include "mm.h"
+#include "mn.h"
+
+//DA Customer table
+UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ //   NOTE:
+ //   The following training hardcode values are example values that were taken from a tilapia motherboard
+ //   with a particular DIMM configuration.  To hardcode your own values, uncomment the appropriate line in
+ //   the table and replace the byte lane values with your own.
+ //
+ //                                                                               ------------------ BYTE LANES ----------------------
+ //                                                                                BL0   BL1   BL2   BL3   BL4   BL5   BL6   Bl7   ECC
+ // Write Data Timing
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ //--------------------------------------------------------------------------------------------------------------------------------------------------
+ // TABLE END
+  NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
+};
+UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
+
+/* ***************************************************************************
+ *   Optional User code to be included into the AGESA build
+ *    These may be 32-bit call-out routines...
+ */
+//AGESA_STATUS
+//AgesaReadSpd (
+//  IN        UINTN                 FcnData,
+//  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+//  )
+//{
+//  /* platform code to read an SPD...  */
+//  return Status;
+//}
+
+
diff --git a/src/mainboard/amd/inagua/chip.h b/src/mainboard/amd/inagua/chip.h
new file mode 100644
index 0000000000..a252705293
--- /dev/null
+++ b/src/mainboard/amd/inagua/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout
new file mode 100644
index 0000000000..8315401c7b
--- /dev/null
+++ b/src/mainboard/amd/inagua/cmos.layout
@@ -0,0 +1,118 @@
+#*****************************************************************************
+# 
+#  This file is part of the coreboot project.
+# 
+#  Copyright (C) 2011 Advanced Micro Devices, Inc.
+# 
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; version 2 of the License.
+# 
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+# 
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
new file mode 100644
index 0000000000..a0a19ea4e1
--- /dev/null
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -0,0 +1,90 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+chip northbridge/amd/agesa_wrapper/family14/root_complex
+        device lapic_cluster 0 on
+                chip cpu/amd/agesa_wrapper/family14
+                  device lapic 0 on end
+                end
+        end
+        device pci_domain 0 on
+                chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+#                       device pci 18.0 on #  northbridge
+                                chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+                                        device pci 0.0 on end # Root Complex
+                                        device pci 1.0 on end # Internal Graphics P2P bridge
+                                        device pci 1.1 on end # Internal Multimedia
+                                        device pci 4.0 on end # PCIE P2P bridge 0x9604
+                                        device pci 5.0 off end # PCIE P2P bridge 0x9605
+                                        device pci 6.0 on end # PCIE P2P bridge 0x9606
+                                        device pci 7.0 off end # PCIE P2P bridge 0x9607
+                                        device pci 8.0 off end # NB/SB Link P2P bridge
+                                end # agesa_wrapper northbridge
+
+                                chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+                                        device pci 11.0 on end # SATA
+                                        device pci 12.0 on end # USB
+                                        device pci 12.1 on end # USB
+                                        device pci 12.2 on end # USB
+                                        device pci 13.0 on end # USB
+                                        device pci 13.1 on end # USB
+                                        device pci 13.2 on end # USB
+                                        device pci 14.0 on # SM
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end
+                                        end # SM
+                                        device pci 14.1 on end # IDE    0x439c
+                                        device pci 14.2 on end # HDA    0x4383
+                                        device pci 14.3 on # LPC        0x439d
+					        chip superio/smsc/kbc1100
+                                                        device pnp 2e.7 on #  Keyboard
+                                                                io 0x60 = 0x60
+                                                                io 0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                                irq 0x72 = 12
+                                                        end
+                                                end # kbc1100
+					end #LPC
+  					device pci 14.4 on end # PCI 0x4384
+	  				device pci 14.5 on end # USB 2
+					device pci 15.0 on end # PCIe PortA
+					device pci 15.1 on end # PCIe PortB
+					device pci 15.2 on end # PCIe PortC
+					device pci 15.3 on end # PCIe PortD
+					register "gpp_configuration" = "4" #1:1:1:1
+		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/cimx_wrapper/sb800
+#                       end #  device pci 18.0
+# These seem unnecessary
+                        device pci 18.0 on end
+                        #device pci 18.0 on end
+                        device pci 18.1 on end
+                        device pci 18.2 on end
+                        device pci 18.3 on end
+                        device pci 18.4 on end
+                        device pci 18.5 on end
+                        device pci 18.6 on end
+                        device pci 18.7 on end
+                end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+        end #pci_domain
+end #northbridge/amd/agesa_wrapper/family14/root_complex
+
diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c
new file mode 100644
index 0000000000..94e63e1bda
--- /dev/null
+++ b/src/mainboard/amd/inagua/dimmSpd.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+/*#pragma optimize ("", off) // for source level debug
+*---------------------------------------------------------------------------
+*
+* SPD address table - porting required
+*/
+
+static const UINT8 spdAddressLookup [2] [2] [4] =  // socket, channel, dimm
+   {
+   // socket 0
+      {
+         {0xA0, 0xA2},  // channel 0 dimms
+         {0xA4, 0xA8},  // channel 1 dimms
+      },
+   // socket 1
+      {
+         {0x00, 0x00},  // channel 0 dimms
+         {0x00, 0x00},  // channel 1 dimms
+      },
+   };
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByteData - read a single SPD byte from any offset
+ */
+
+static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
+   {
+   unsigned int status;
+   UINT64 limit;
+
+   address |= 1; // set read bit
+   
+   __outbyte (iobase + 0, 0xFF);                // clear error status
+   __outbyte (iobase + 1, 0x1F);                // clear error status
+   __outbyte (iobase + 3, offset);              // offset in eeprom
+   __outbyte (iobase + 4, address);             // slave address and read bit
+   __outbyte (iobase + 2, 0x48);                // read byte command
+
+   // time limit to avoid hanging for unexpected error status (should never happen)
+   limit = __rdtsc () + 2000000000 / 10;
+   for (;;)
+      {
+      status = __inbyte (iobase);
+      if (__rdtsc () > limit) break;
+      if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+      if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
+      break;
+      }
+
+   buffer [0] = __inbyte (iobase + 5);
+   if (status == 2) status = 0;                      // check for done with no errors
+   return status;
+   }
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByte - read a single SPD byte from the default offset
+ *                 this function is faster function readSmbusByteData
+ */
+
+static int readSmbusByte (int iobase, int address, char *buffer)
+   {
+   unsigned int status;
+   UINT64 limit;
+
+   __outbyte (iobase + 0, 0xFF);                // clear error status
+   __outbyte (iobase + 2, 0x44);                // read command
+
+   // time limit to avoid hanging for unexpected error status
+   limit = __rdtsc () + 2000000000 / 10;
+   for (;;)
+      {
+      status = __inbyte (iobase);
+      if (__rdtsc () > limit) break;
+      if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+      if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
+      break;
+      }
+
+   buffer [0] = __inbyte (iobase + 5);
+   if (status == 2) status = 0;                      // check for done with no errors
+   return status;
+   }
+
+/*---------------------------------------------------------------------------
+ *
+ * readspd - Read one or more SPD bytes from a DIMM.
+ *           Start with offset zero and read sequentially.
+ *           Optimization relies on autoincrement to avoid 
+ *           sending offset for every byte.
+ *          Reads 128 bytes in 7-8 ms at 400 KHz.
+ */
+
+static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
+   {
+   int index, error;
+
+   /* read the first byte using offset zero */
+   error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+   if (error) return error;
+
+   /* read the remaining bytes using auto-increment for speed */
+   for (index = 1; index < count; index++)
+      {
+      error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
+      if (error) return error;
+      }
+   
+   return 0;
+   }
+
+static void writePmReg (int reg, int data)
+   {
+   __outbyte (0xCD6, reg);
+   __outbyte (0xCD7, data);
+   }
+
+static void setupFch (int ioBase)
+   {
+   writePmReg (0x2D, ioBase >> 8);
+   writePmReg (0x2C, ioBase | 1);
+   writePmReg (0x29, 0x80);
+   writePmReg (0x28, 0x61);
+   __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
+   }
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
+   {
+   int spdAddress, ioBase;
+
+   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR; 
+   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR; 
+   if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
+   
+   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; 
+   if (spdAddress == 0) return AGESA_ERROR;
+   ioBase = 0xB00;
+   setupFch (ioBase);
+   return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
+   }
diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl
new file mode 100644
index 0000000000..d7506c9ffb
--- /dev/null
+++ b/src/mainboard/amd/inagua/dsdt.asl
@@ -0,0 +1,1807 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"AMD   ",               /* OEMID */
+	"INAGUA  ",	     /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include "../../../arch/x86/acpi/debug.asl" */	/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+	} /* End _PR scope */
+
+	/* PIC IRQ mapping registers, C00h-C01h. */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PIRA, 0x00000008,	/* Index 0 */
+		PIRB, 0x00000008,	/* Index 1 */
+		PIRC, 0x00000008,	/* Index 2 */
+		PIRD, 0x00000008,	/* Index 3 */
+		PIRE, 0x00000008,	/* Index 4 */
+		PIRF, 0x00000008,	/* Index 5 */
+		PIRG, 0x00000008,	/* Index 6 */
+		PIRH, 0x00000008,	/* Index 7 */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk. TODO: should be 0x60 */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve){
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+		Method(CIRQ, 0x00, NotSerialized){
+			Store(0, PIRA)
+			Store(0, PIRB)
+			Store(0, PIRC)
+			Store(0, PIRD)
+			Store(0, PIRE)
+			Store(0, PIRF)
+			Store(0, PIRG)
+			Store(0, PIRH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PIRA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PIRA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PIRB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PIRB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PIRC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PIRC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIRD) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIRD)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRD, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRD)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PIRE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PIRE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PIRF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PIRF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PIRG) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PIRG)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRG, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRG)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PIRH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PIRH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIRH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIRH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			/* Notify (\_TZ.TZ00, 0x80) */
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	#include "acpi/usb.asl"
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			External (TOM1)
+			External (TOM2)
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+			/* GPP */
+			Device(PBR9) {
+				Name(_ADR, 0x00090000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS9) }   /* APIC mode */
+					Return (PS9)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR9 */
+
+			Device(PBRa) {
+				Name(_ADR, 0x000A0000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APSa) }   /* APIC mode */
+					Return (PSa)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBRa */
+
+			Device(PE20) {
+				Name(_ADR, 0x00150000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE0) }   /* APIC mode */
+					Return (PE0)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE20 */
+			Device(PE21) {
+				Name(_ADR, 0x00150001)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE1) }   /* APIC mode */
+					Return (PE1)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE21 */
+			Device(PE22) {
+				Name(_ADR, 0x00150002)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE2) }   /* APIC mode */
+					Return (APE2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE22 */
+			Device(PE23) {
+				Name(_ADR, 0x00150003)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APE3) }   /* APIC mode */
+					Return (PE3)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PE23 */
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00110000)
+				#include "acpi/sata.asl"
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00120000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00120002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00160000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UOH6) {
+				Name(_ADR, 0x00160002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00140005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#if 0
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+#endif
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* length */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+
+#if 0
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00000000,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00000000,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+#endif
+                                /* memory space for PCI BARs below 4GB */
+                                Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+#if 0
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM1, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	Subtract(TOM2, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+#endif
+				CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+                                CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+                                /*
+                                 * Declare memory between TOM1 and 4GB as available
+                                 * for PCI MMIO.
+                                 * Use ShiftLeft to avoid 64bit constant (for XP).
+                                 * This will work even if the OS does 32bit arithmetic, as
+                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
+                                 * result as 64bit (0x100000000 - TOM1).
+                                 */
+                                Store(TOM1, MM1B)
+                                ShiftLeft(0x10000000, 4, Local0)
+                                Subtract(Local0, TOM1, Local0)
+                                Store(Local0, MM1L)
+
+				Return(CRES) /* note to change the Name buffer */
+			} /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+#if 0
+	/* SMBUS Support */
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+#endif
+}
+/* End of ASL file */
diff --git a/src/mainboard/amd/inagua/fadt.c b/src/mainboard/amd/inagua/fadt.c
new file mode 100644
index 0000000000..c31a0e4cda
--- /dev/null
+++ b/src/mainboard/amd/inagua/fadt.c
@@ -0,0 +1,207 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+//#include "../../../southbridge/amd/sb800/sb800.h"
+
+/*extern*/ u16 pm_base = 0x800;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of sb800. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+#define ACPI_PM_EVT_BLK		(pm_base + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK	(pm_base + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK	(pm_base + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK		(pm_base + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK		(pm_base + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTORL	(pm_base + 0x08) /* 6 bytes */
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	pm_base &= 0xFFFF;
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, OEM_ID, 6);
+  memcpy(header->oem_table_id, "AMD     ", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
+	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
+	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
+	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
+	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
+	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
+	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
+	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
+	pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+
+	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
+	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
+
+	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
+	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+
+	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
+					* the contents of the PM registers at
+					* index 60-6B to decode ACPI I/O address.
+					* AcpiSmiEn & SmiCmdEn*/
+	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
+	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
+	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+
+}
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
new file mode 100644
index 0000000000..43b9013d8d
--- /dev/null
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/amd/amdfam14.h>
+
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+u8 bus_isa;
+u8 bus_sb800[3];
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+  0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+  0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_sb800;
+
+//KZ [092110]extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+
+
+
+void get_bus_conf(void)
+{
+  u32 status;
+
+  device_t dev;
+  int i, j;
+
+  if (get_bus_conf_done == 1)
+    return;   /* do it only once */
+
+  get_bus_conf_done = 1;
+
+/*
+ * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
+ * but functionally within the coreboot model, this is the best place to make the
+ * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
+ * after the decision about S3 resume is made, and before the system tables are 
+ * written into RAM.  The routine that is responsible for writing the tables is 
+ * "write_tables", called near the end of "hardwaremain".  There is no platform 
+ * specific entry point between the S3 resume decision point and the call to 
+ * "write_tables", and the next platform specific entry points are the calls to 
+ * the ACPI table write functions.  The first of ose would seem to be the right 
+ * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * called before the ACPI tables are written.  This routine is called at the beginning
+ * of each of the write functions called prior to the ACPI write functions, so this
+ * becomes the best place for this call.
+ */
+  status = agesawrapper_amdinitlate(); 
+  if(status) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+  }
+  
+  sbdn_sb800 = 0;
+
+  for (i = 0; i < 3; i++) {
+    bus_sb800[i] = 0;
+  }
+
+  for (i = 0; i < 256; i++) {
+    bus_type[i] = 0; /* default ISA bus. */
+  }
+
+
+  bus_type[0] = 1;  /* pci */
+
+//  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+  bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
+
+  /* sb800 */
+  dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+
+
+
+  if (dev) {
+    bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+    bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+    bus_isa++;
+    for (j = bus_sb800[1]; j < bus_isa; j++)
+      bus_type[j] = 1;
+  }
+
+  for (i = 0; i < 4; i++) {
+    dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
+    if (dev) {
+      bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+      bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+      bus_isa++;
+    }
+  }
+  for (j = bus_sb800[2]; j < bus_isa; j++)
+    bus_type[j] = 1;
+
+
+  /* I/O APICs:   APIC ID Version State   Address */
+  bus_isa = 10;
+}
diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c
new file mode 100644
index 0000000000..a8ea5aa7e1
--- /dev/null
+++ b/src/mainboard/amd/inagua/irq_tables.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+//#include <cpu/amd/amdfam10_sysconf.h>
+
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+extern u8 bus_isa;
+extern u8 bus_sb800[2];
+extern unsigned long sbdn_sb800;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb800[0];
+	pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+
+
+
+	slot_num++;
+
+
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+
+}
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
new file mode 100644
index 0000000000..e5025b6a54
--- /dev/null
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+//#include <southbridge/amd/sb800/sb800.h>
+#include "chip.h"
+
+//#define SMBUS_IO_BASE 0x6000
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+uint64_t uma_memory_base, uma_memory_size;
+
+/*************************************************
+* enable the dedicated function in inagua board.
+*************************************************/
+static void inagua_enable(device_t dev)
+{
+	printk(BIOS_INFO, "Mainboard Inagua Enable. dev=0x%p\n", dev);
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+	uint32_t sys_mem;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	/* refer to UMA Size Consideration in Family14h BKDG. */
+	sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
+	if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) {
+		uma_memory_size = 0x18000000;	/* >= 2G memory, 384M recommended UMA */
+	}
+	else {
+	  if (sys_mem >= 0x40000000) {
+		  uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
+	  }
+	  else {
+		  uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
+	  }
+	}
+	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+		    __func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 0x10000000;	/* 256M recommended UMA */
+	uma_memory_base = 0x30000000;	/* 1GB  system memory supported */
+#endif
+
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+ 	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+		    uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			    uma_memory_size);
+#endif
+	return 0;
+}
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("AMD INAGUA Mainboard")
+	.enable_dev = inagua_enable,
+};
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
new file mode 100644
index 0000000000..86f08db7c1
--- /dev/null
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -0,0 +1,247 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+
+#define IO_APIC_ID    CONFIG_MAX_PHYSICAL_CPUS + 1
+extern u8 bus_sb800[2];
+
+
+extern u32 bus_type[256];
+extern u32 sbdn_sb800;
+u32 apicid_sb800;
+
+u8 picr_data[] = {
+  0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
+  0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 
+  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x0B,0x0A,0x0B,0x05
+};
+u8 intr_data[] = {
+  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
+  0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+  mc->mpc_length += length;
+  mc->mpc_entry_count++;
+}
+static void my_smp_write_bus(struct mp_config_table *mc,
+  unsigned char id, const char *bustype)
+{
+  struct mpc_config_bus *mpc;
+  mpc = smp_next_mpc_entry(mc);
+  memset(mpc, '\0', sizeof(*mpc));
+  mpc->mpc_type = MP_BUS;
+  mpc->mpc_busid = id;
+  memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+  smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+static void *smp_write_config_table(void *v)
+{
+  struct mp_config_table *mc;
+  int bus_isa;
+  int boot_apic_id;
+  unsigned apic_version;
+  unsigned cpu_features;
+  unsigned cpu_feature_flags;
+  struct cpuid_result result;
+  unsigned long cpu_flag;
+
+  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+  mptable_init(mc, LAPIC_ADDR);
+  memcpy(mc->mpc_oem, "AMD     ", 8);
+
+  /*Inagua used dure core cpu with one die */
+  boot_apic_id = lapicid();
+  apic_version = lapic_read(LAPIC_LVR) & 0xff;
+  result = cpuid(1);
+  cpu_features = result.eax;
+  cpu_feature_flags = result.edx;
+  cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
+  smp_write_processor(mc,
+      0, apic_version,
+      cpu_flag, cpu_features, cpu_feature_flags
+    );
+  
+  cpu_flag = MPC_CPU_ENABLED;
+  smp_write_processor(mc,
+      1, apic_version,
+      cpu_flag, cpu_features, cpu_feature_flags
+    );
+
+  get_bus_conf();
+
+  //mptable_write_buses(mc, NULL, &bus_isa);
+  my_smp_write_bus(mc, 0, "PCI   ");
+  my_smp_write_bus(mc, 1, "PCI   ");
+  bus_isa = 0x02;
+  my_smp_write_bus(mc, bus_isa, "ISA   ");
+
+  /* I/O APICs:   APIC ID Version State   Address */
+  
+  device_t dev;
+  u32 dword;
+  u8 byte;
+    
+  dword = 0;
+  dword = pm_ioread(0x34) & 0xF0;
+  dword |= (pm_ioread(0x35) & 0xFF) << 8;
+  dword |= (pm_ioread(0x36) & 0xFF) << 16;
+  dword |= (pm_ioread(0x37) & 0xFF) << 24;
+  /* Set IO APIC ID onto IO_APIC_ID */
+  write32 (dword, 0x00);
+  write32 (dword + 0x10, IO_APIC_ID << 24);
+  apicid_sb800 = IO_APIC_ID;
+  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+  
+  /* PIC IRQ routine */
+  for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+    outb(byte, 0xC00);
+    outb(picr_data[byte], 0xC01);
+  }
+  
+  /* APIC IRQ routine */
+  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+    outb(byte | 0x80, 0xC00);
+    outb(intr_data[byte], 0xC01);
+  }
+
+    /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+  //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+  /*I/O Ints:          Type    Trigger             Polarity               Bus ID   IRQ  APIC ID       PIN# */
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_sb800, 0x0);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sb800, 0x1);
+  smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x2, apicid_sb800, 0x2);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_sb800, 0x3);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_sb800, 0x4);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  0, 0x49, apicid_sb800, 0x11);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_sb800, 0x6);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_sb800, 0x7);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_sb800, 0x8);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_sb800, 0x9);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0xa, apicid_sb800, 0xa);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0x1c, apicid_sb800, 0x13);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_sb800, 0xc);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_sb800, 0xd);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_sb800, 0xe);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_sb800, 0xf);
+
+  /* PCI interrupts are level triggered, and are
+   * associated with a specific bus/device/function tuple.
+   */
+#define PCI_INT(bus, dev, int_sign, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+
+  /* SMBUS */
+  PCI_INT(0x0, 0x14, 0x0, 0x10);
+  
+  /* HD Audio */
+  PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+  
+  /* USB */
+  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); 
+  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+  PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+  /* sata */
+  PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+
+  /* on board NIC & Slot PCIE.  */
+  
+  /* PCI slots */
+  /* PCI_SLOT 0. */
+  PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+  PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+  PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+  PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+  /* PCI_SLOT 1. */
+  PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+  PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+  PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+  PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+  /* PCI_SLOT 2. */
+  PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+  PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+  PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+  PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+  PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
+  PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
+  PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+
+  /* PCIe Lan*/
+  PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+  /* FCH PCIe PortA */
+  PCI_INT(0x0, 0x15, 0x0, 0x10);
+  /* FCH PCIe PortB */
+  PCI_INT(0x0, 0x15, 0x1, 0x11);
+  /* FCH PCIe PortC */
+  PCI_INT(0x0, 0x15, 0x2, 0x12);
+  /* FCH PCIe PortD */
+  PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+  IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+  IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+  /* There is no extension information... */
+
+  /* Compute the checksums */
+  mc->mpe_checksum =
+      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+         mc, smp_next_mpe_entry(mc));
+  return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+  void *v;
+  v = smp_write_floating_table(addr);
+  return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/amd/inagua/pmio.c b/src/mainboard/amd/inagua/pmio.c
new file mode 100644
index 0000000000..baded54ba6
--- /dev/null
+++ b/src/mainboard/amd/inagua/pmio.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/io.h>	/*inb, outb*/
+#include "pmio.h"
+
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
+{
+	outb(reg, port_base);
+	outb(value, port_base + 1);
+}
+
+static u8 pmio_read_index(u16 port_base, u8 reg)
+{
+	outb(reg, port_base);
+	return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+	pmio_write_index(PM_INDEX, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+	return pmio_read_index(PM_INDEX, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+	pmio_write_index(PM2_INDEX, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+	return pmio_read_index(PM2_INDEX, reg);
+}
+
diff --git a/src/mainboard/amd/inagua/pmio.h b/src/mainboard/amd/inagua/pmio.h
new file mode 100644
index 0000000000..207fdc24ab
--- /dev/null
+++ b/src/mainboard/amd/inagua/pmio.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _PMIO_H_
+#define _PMIO_H_
+
+#define PM_INDEX	0xCD6
+#define PM_DATA		0xCD7
+#define PM2_INDEX	0xCD0
+#define PM2_DATA	0xCD1
+
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+#endif
diff --git a/src/mainboard/amd/inagua/reset.c b/src/mainboard/amd/inagua/reset.c
new file mode 100644
index 0000000000..36bc6e0f17
--- /dev/null
+++ b/src/mainboard/amd/inagua/reset.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <reset.h>
+#include <arch/io.h>		/*inb, outb*/
+#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes;
+	u32 htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for(i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
new file mode 100644
index 0000000000..cbebf07e0f
--- /dev/null
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include "superio/smsc/kbc1100/kbc1100_early_init.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "pc80/i8254.c"
+#include "pc80/i8259.c"
+#include "SbEarly.h"
+#include "SBPLATFORM.h"
+#include <arch/cpu.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
+u32 agesawrapper_amdinitmmio (void);
+u32 agesawrapper_amdinitreset (void);
+u32 agesawrapper_amdinitearly (void);
+u32 agesawrapper_amdinitenv (void);
+u32 agesawrapper_amdinitlate (void);
+u32 agesawrapper_amdinitpost (void);
+u32 agesawrapper_amdinitmid (void);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+  u32 val;
+
+  if (!cpu_init_detectedx && boot_cpu()) {
+    post_code(0x30);
+    sb_poweron_init();
+
+    post_code(0x31);
+    kbc1100_early_init(CONFIG_SIO_PORT);
+    uart_init();
+    console_init();
+  }
+
+  /* Halt if there was a built in self test failure */
+  post_code(0x34);
+  report_bist_failure(bist);
+
+  // Load MPB
+  val = cpuid_eax(1);
+  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+  post_code(0x35);
+  val = agesawrapper_amdinitmmio();
+
+  post_code(0x37);
+  val = agesawrapper_amdinitreset();
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+  }
+
+  post_code(0x38);
+  printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+
+  post_code(0x39);
+  val = agesawrapper_amdinitearly ();
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+  post_code(0x40);
+  val = agesawrapper_amdinitpost ();
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+  post_code(0x41);
+  val = agesawrapper_amdinitenv ();
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+  /* Initialize i8259 pic */
+  post_code(0x41);
+  setup_i8259 ();
+
+  /* Initialize i8254 timers */
+  post_code(0x42);
+  setup_i8254 ();
+
+  post_code(0x50);
+  copy_and_run(0);
+
+  post_code(0x54);  // Should never see this post code.
+}
+