Fix Fam14 mainboard whitespace

Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
changes

Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/515
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

2 files changed, 592 insertions, 597 deletions

diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index cc37ed24b0..6450f35172 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -38,15 +38,15 @@ extern u32 apicid_sb800;
 static void dump_mem(u32 start, u32 end)
 {
 
-  u32 i;
-  print_debug("dump_mem:");
-  for (i = start; i < end; i++) {
-    if ((i & 0xf) == 0) {
-      printk(BIOS_DEBUG, "\n%08x:", i);
-    }
-    printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
-  }
-  print_debug("\n");
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
 }
 #endif
 
@@ -56,197 +56,197 @@ extern const unsigned char AmlCode_ssdt[];
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-  /* Just a dummy */
-  return current;
+	/* Just a dummy */
+	return current;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
 
-  /* create all subtables for processors */
-  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
-  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
+	/* create all subtables for processors */
+	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
+	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
 
-  /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
-             IO_APIC_ADDR, 0);
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
+			 IO_APIC_ADDR, 0);
 
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+			current, 0, 0, 2, 0);
 
-  /* 0: mean bus 0--->ISA */
-  /* 0: PIC 0 */
-  /* 2: APIC 2 */
-  /* 5 mean: 0101 --> Edige-triggered, Active high */
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
 
-  /* create all subtables for processors */
-  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
-  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
-  /* 1: LINT1 connect to NMI */
+	/* create all subtables for processors */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+	/* 1: LINT1 connect to NMI */
 
-  return current;
+	return current;
 }
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-  // Not implemented
-  return current;
+	// Not implemented
+	return current;
 }
 
 unsigned long acpi_fill_srat(unsigned long current)
 {
-  /* No NUMA, no SRAT */
-  return current;
+	/* No NUMA, no SRAT */
+	return current;
 }
 
 unsigned long write_acpi_tables(unsigned long start)
 {
-  unsigned long current;
-  acpi_rsdp_t *rsdp;
-  acpi_rsdt_t *rsdt;
-  acpi_hpet_t *hpet;
-  acpi_madt_t *madt;
-  acpi_srat_t *srat;
-  acpi_slit_t *slit;
-  acpi_fadt_t *fadt;
-  acpi_facs_t *facs;
-  acpi_header_t *dsdt;
-  acpi_header_t *ssdt;
-
-  get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
-
-  /* Align ACPI tables to 16 bytes */
-  start = (start + 0x0f) & -0x10;
-  current = start;
-
-  printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
-  /* We need at least an RSDP and an RSDT Table */
-  rsdp = (acpi_rsdp_t *) current;
-  current += sizeof(acpi_rsdp_t);
-  rsdt = (acpi_rsdt_t *) current;
-  current += sizeof(acpi_rsdt_t);
-
-  /* clear all table memory */
-  memset((void *)start, 0, current - start);
-
-  acpi_write_rsdp(rsdp, rsdt, NULL);
-  acpi_write_rsdt(rsdt);
-
-  /* DSDT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-  dsdt = (acpi_header_t *)current; // it will used by fadt
-  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-  current += dsdt->length;
-  memcpy(dsdt, &AmlCode, dsdt->length);
-  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
-  /* FACS */ // it needs 64 bit alignment
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-  facs = (acpi_facs_t *) current; // it will be used by fadt
-  current += sizeof(acpi_facs_t);
-  acpi_create_facs(facs);
-
-  /* FADT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
-  fadt = (acpi_fadt_t *) current;
-  current += sizeof(acpi_fadt_t);
-
-  acpi_create_fadt(fadt, facs, dsdt);
-  acpi_add_table(rsdp, fadt);
-
-  /*
-   * We explicitly add these tables later on:
-   */
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+
+	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* DSDT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:  * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FADT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
 #if 0 // Don't need HPET table.
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
-  hpet = (acpi_hpet_t *) current;
-  current += sizeof(acpi_hpet_t);
-  acpi_create_hpet(hpet);
-  acpi_add_table(rsdp, hpet);
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
 #endif
 
-  /* If we want to use HPET Timers Linux wants an MADT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
-  madt = (acpi_madt_t *) current;
-  acpi_create_madt(madt);
-  current += madt->header.length;
-  acpi_add_table(rsdp, madt);
-
-  /* SRAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
-  srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
-  if (srat != NULL) {
-    memcpy(current, srat, srat->header.length);
-    srat = (acpi_srat_t *) current;
-    //acpi_create_srat(srat);
-    current += srat->header.length;
-    acpi_add_table(rsdp, srat);
-  }
-
-  /* SLIT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
-  slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
-  if (slit != NULL) {
-    memcpy(current, slit, slit->header.length);
-    slit = (acpi_slit_t *) current;
-    //acpi_create_slit(slit);
-    current += slit->header.length;
-    acpi_add_table(rsdp, slit);
-  }
-
-  /* SSDT */
-  current   = ( current + 0x0f) & -0x10;
-  printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-  ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-  if (ssdt != NULL) {
-    memcpy(current, ssdt, ssdt->length);
-    ssdt = (acpi_header_t *) current;
-    current += ssdt->length;
-  }
-  else {
-    ssdt = (acpi_header_t *) current;
-    memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-    current += ssdt->length;
-    memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-   /* recalculate checksum */
-    ssdt->checksum = 0;
-    ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
-  }
-  acpi_add_table(rsdp,ssdt);
-
-  printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+	if (srat != NULL) {
+		memcpy(current, srat, srat->header.length);
+		srat = (acpi_srat_t *) current;
+		//acpi_create_srat(srat);
+		current += srat->header.length;
+		acpi_add_table(rsdp, srat);
+	}
+
+	/* SLIT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+	if (slit != NULL) {
+		memcpy(current, slit, slit->header.length);
+		slit = (acpi_slit_t *) current;
+		//acpi_create_slit(slit);
+		current += slit->header.length;
+		acpi_add_table(rsdp, slit);
+	}
+
+	/* SSDT */
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+		memcpy(current, ssdt, ssdt->length);
+		ssdt = (acpi_header_t *) current;
+		current += ssdt->length;
+	}
+	else {
+		ssdt = (acpi_header_t *) current;
+		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+		current += ssdt->length;
+		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+		 /* recalculate checksum */
+		ssdt->checksum = 0;
+		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	}
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
 
 #if DUMP_ACPI_TABLES == 1
-  printk(BIOS_DEBUG, "rsdp\n");
-  dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-  printk(BIOS_DEBUG, "rsdt\n");
-  dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-  printk(BIOS_DEBUG, "madt\n");
-  dump_mem(madt, ((void *)madt) + madt->header.length);
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-  printk(BIOS_DEBUG, "srat\n");
-  dump_mem(srat, ((void *)srat) + srat->header.length);
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-  printk(BIOS_DEBUG, "slit\n");
-  dump_mem(slit, ((void *)slit) + slit->header.length);
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-  printk(BIOS_DEBUG, "ssdt\n");
-  dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-  printk(BIOS_DEBUG, "fadt\n");
-  dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-  printk(BIOS_INFO, "ACPI: done.\n");
-  return current;
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
 }
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index df5cd1e9a9..727436cd9d 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -17,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
+/*-----------------------------------------------------------------------------
+ *						M O D U L E S		U S E D
+ *-----------------------------------------------------------------------------
  */
 
 #include <stdint.h>
@@ -39,503 +39,498 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *					D E F I N I T I O N S		A N D		M A C R O S
+ *------------------------------------------------------------------------------
  */
 
 /* ACPI table pointers returned by AmdInitLate */
-VOID *DmiTable    = NULL;
-VOID *AcpiPstate  = NULL;
-VOID *AcpiSrat    = NULL;
-VOID *AcpiSlit    = NULL;
+VOID *DmiTable		= NULL;
+VOID *AcpiPstate	= NULL;
+VOID *AcpiSrat		= NULL;
+VOID *AcpiSlit		= NULL;
 
-VOID *AcpiWheaMce = NULL;
-VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib    = NULL;
+VOID *AcpiWheaMce	= NULL;
+VOID *AcpiWheaCmc	= NULL;
+VOID *AcpiAlib		= NULL;
 
 
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *				T Y P E D E F S		 A N D		 S T R U C T U R E S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *	P R O T O T Y P E S		 O F		 L O C A L		 F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						E X P O R T E D		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*---------------------------------------------------------------------------------------
- *                          L O C A L    F U N C T I O N S
- *---------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						L O C A L		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 UINT32
 agesawrapper_amdinitcpuio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-
-  /* Enable MMIO on AMD CPU Address Map Controller */
-
-  /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00000B00;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = 0x00000A03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  /* Set TOM-DFFFFFFF to Node0 Link0. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00DFFF00;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
-  MsrReg = (MsrReg >> 8) | 3;
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
-  PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
-  PciData = 0x00FFFF00 | 0x80;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
-  PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
-  PciData = 0x0000F000;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000013;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	/* Enable MMIO on AMD CPU Address Map Controller */
+
+	/* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciData = 0x00000B00;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciData = 0x00000A03;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Set TOM-DFFFFFFF to Node0 Link0. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciData = 0x00DFFF00;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+	MsrReg = (MsrReg >> 8) | 3;
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciData = (UINT32)MsrReg;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	/* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
+	PciData = 0x00FFFF00 | 0x80;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
+	PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciData = 0x0000F000;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciData = 0x00000013;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitmmio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-
-  /*
-   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-   Address MSR register.
-  */
-  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
-  LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
-  /*
-   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-  */
-  LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-  MsrReg = MsrReg | 0x0000400000000000;
-  LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
-  /* Set Ontario Link Data */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
-  PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
-  PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-
-  /* Set ROM cache onto WP to decrease post time */
-  MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
-  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
-  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	/*
+	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	 Address MSR register.
+	*/
+	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+	/*
+	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	*/
+	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+	MsrReg = MsrReg | 0x0000400000000000;
+	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+	/* Set Ontario Link Data */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+	PciData = 0x01308002;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+	PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+
+	/* Set ROM cache onto WP to decrease post time */
+	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
+	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitreset (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_RESET_PARAMS AmdResetParams;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-
-  LibAmdMemFill (&AmdResetParams,
-                 0,
-                 sizeof (AMD_RESET_PARAMS),
-                 &(AmdResetParams.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
-  AmdParamStruct.AllocationMethod = ByHost;
-  AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
-  AmdParamStruct.NewStructPtr = &AmdResetParams;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = NULL;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  AmdResetParams.HtConfig.Depth = 0;
-
-  status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_RESET_PARAMS AmdResetParams;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+
+	LibAmdMemFill (&AmdResetParams,
+					0,
+					sizeof (AMD_RESET_PARAMS),
+					&(AmdResetParams.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+	AmdParamStruct.AllocationMethod = ByHost;
+	AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+	AmdParamStruct.NewStructPtr = &AmdResetParams;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = NULL;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	AmdResetParams.HtConfig.Depth = 0;
+
+	status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	return (UINT32)status;
  }
 
 UINT32
 agesawrapper_amdinitearly (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-
-  AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
-  OemCustomizeInitEarly (AmdEarlyParamsPtr);
-
-  status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_EARLY_PARAMS	 *AmdEarlyParamsPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+
+	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+	OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+	status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitpost (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  UINT16                  i;
-  UINT32          *HeadPtr;
-  AMD_INTERFACE_PARAMS  AmdParamStruct;
-  BIOS_HEAP_MANAGER    *BiosManagerPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  /* Initialize heap space */
-  BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
-
-  HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-  for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-  {
-    *HeadPtr = 0x00000000;
-    HeadPtr++;
-  }
-  BiosManagerPtr->StartOfAllocatedNodes = 0;
-  BiosManagerPtr->StartOfFreedNodes = 0;
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	UINT16					i;
+	UINT32					*HeadPtr;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	BIOS_HEAP_MANAGER		*BiosManagerPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	/* Initialize heap space */
+	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+	{
+		*HeadPtr = 0x00000000;
+		HeadPtr++;
+	}
+	BiosManagerPtr->StartOfAllocatedNodes = 0;
+	BiosManagerPtr->StartOfFreedNodes = 0;
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitenv (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  PCI_ADDR             PciAddress;
-  UINT32               PciValue;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  /* Initialize Subordinate Bus Number and Secondary Bus Number
-   * In platform BIOS this address is allocated by PCI enumeration code
-     Modify D1F0x18
-   */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-  /* Write to D1F0x18 */
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x00010100;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Legacy Bridge Mode
-  *  Modify B1D5F0x18
-  */
-  PciAddress.Address.Bus = 1;
-  PciAddress.Address.Device = 5;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Legacy Bridge Mode
-  * Modify B1D5F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Pcie Mode
-  *  Modify B0D1F0x18
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Pcie Mode
-  *  Modify B0D1F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-
-  /* Initialize MMIO Base and Limit Address
-  *  Modify B0D1F0x20
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x20;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96009600;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Prefetchable Memory Limit and Base
-  *  Modify B0D1F0x24
-  */
-  PciAddress.Address.Register = 0x24;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x8FF18001;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	PCI_ADDR			 PciAddress;
+	UINT32				 PciValue;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	/* Initialize Subordinate Bus Number and Secondary Bus Number
+	 * In platform BIOS this address is allocated by PCI enumeration code
+		 Modify D1F0x18
+	 */
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+	/* Write to D1F0x18 */
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x00010100;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Legacy Bridge Mode
+	*	Modify B1D5F0x18
+	*/
+	PciAddress.Address.Bus = 1;
+	PciAddress.Address.Device = 5;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Legacy Bridge Mode
+	* Modify B1D5F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Pcie Mode
+	*	Modify B0D1F0x18
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Pcie Mode
+	*	Modify B0D1F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+
+	/* Initialize MMIO Base and Limit Address
+	*	Modify B0D1F0x20
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x20;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96009600;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Prefetchable Memory Limit and Base
+	*	Modify B0D1F0x24
+	*/
+	PciAddress.Address.Register = 0x24;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x8FF18001;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 VOID *
 agesawrapper_getlateinitptr (
-  int pick
-  )
+	int pick
+	)
 {
-  switch (pick) {
-    case PICK_DMI:
-      return DmiTable;
-
-    case PICK_PSTATE:
-      return AcpiPstate;
-
-    case PICK_SRAT:
-      return AcpiSrat;
-
-    case PICK_SLIT:
-      return AcpiSlit;
-    case PICK_WHEA_MCE:
-      return AcpiWheaMce;
-    case PICK_WHEA_CMC:
-      return AcpiWheaCmc;
-    case PICK_ALIB:
-      return AcpiAlib;
-    default:
-      return NULL;
-  }
+	switch (pick) {
+		case PICK_DMI:
+			return DmiTable;
+		case PICK_PSTATE:
+			return AcpiPstate;
+		case PICK_SRAT:
+			return AcpiSrat;
+		case PICK_SLIT:
+			return AcpiSlit;
+		case PICK_WHEA_MCE:
+			return AcpiWheaMce;
+		case PICK_WHEA_CMC:
+			return AcpiWheaCmc;
+		case PICK_ALIB:
+			return AcpiAlib;
+		default:
+			return NULL;
+	}
 }
 
 UINT32
 agesawrapper_amdinitmid (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
 
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  agesawrapper_amdinitcpuio ();
+	/* Enable MMIO on AMD CPU Address Map Controller */
+	agesawrapper_amdinitcpuio ();
 
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-  AmdCreateStruct (&AmdParamStruct);
+	AmdCreateStruct (&AmdParamStruct);
 
-  status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
+	status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
 
-  return (UINT32)status;
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitlate (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
-
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdInitLate (&AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+					0,
+					sizeof (AMD_LATE_PARAMS),
+					&(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdInitLate (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	DmiTable		= AmdLateParams.DmiTable;
+	AcpiPstate		= AmdLateParams.AcpiPState;
+	AcpiSrat		= AmdLateParams.AcpiSrat;
+	AcpiSlit		= AmdLateParams.AcpiSlit;
+	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
+	AcpiAlib		= AmdLateParams.AcpiAlib;
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Data,
-  VOID *ConfigPtr
-  )
+	UINT32 Data,
+	VOID *ConfigPtr
+	)
 {
-  AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
-
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdLateRunApTask (&AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+					0,
+					sizeof (AMD_LATE_PARAMS),
+					&(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdLateRunApTask (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	DmiTable		= AmdLateParams.DmiTable;
+	AcpiPstate		= AmdLateParams.AcpiPState;
+	AcpiSrat		= AmdLateParams.AcpiSrat;
+	AcpiSlit		= AmdLateParams.AcpiSlit;
+	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
+	AcpiAlib		= AmdLateParams.AcpiAlib;
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdreadeventlog (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  EVENT_PARAMS AmdEventParams;
-
-  LibAmdMemFill (&AmdEventParams,
-                 0,
-                 sizeof (EVENT_PARAMS),
-                 &(AmdEventParams.StdHeader));
-
-  AmdEventParams.StdHeader.AltImageBasePtr = 0;
-  AmdEventParams.StdHeader.CalloutPtr = NULL;
-  AmdEventParams.StdHeader.Func = 0;
-  AmdEventParams.StdHeader.ImageBasePtr = 0;
-  Status = AmdReadEventLog (&AmdEventParams);
-  while (AmdEventParams.EventClass != 0) {
-    printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
-    printk(BIOS_DEBUG,"  Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
-    printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
-    Status = AmdReadEventLog (&AmdEventParams);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	EVENT_PARAMS AmdEventParams;
+
+	LibAmdMemFill (&AmdEventParams,
+					0,
+					sizeof (EVENT_PARAMS),
+					&(AmdEventParams.StdHeader));
+
+	AmdEventParams.StdHeader.AltImageBasePtr = 0;
+	AmdEventParams.StdHeader.CalloutPtr = NULL;
+	AmdEventParams.StdHeader.Func = 0;
+	AmdEventParams.StdHeader.ImageBasePtr = 0;
+	Status = AmdReadEventLog (&AmdEventParams);
+	while (AmdEventParams.EventClass != 0) {
+		printk(BIOS_DEBUG,"\nEventLog:	EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+		printk(BIOS_DEBUG,"	Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+		printk(BIOS_DEBUG,"	Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+		Status = AmdReadEventLog (&AmdEventParams);
+	}
+
+	return (UINT32)Status;
 }