diff options
| author | Kerry Sheh <shekairui@gmail.com> | 2012-01-19 13:18:36 +0800 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-02-07 00:06:07 +0100 |
| commit | 01f7ab93359ae0fee5784d35effbcbe0b596df18 (patch) | |
| tree | b7dbaeda0626de4680a1772c39c13691f6b66453 /src/mainboard/amd/inagua/devicetree.cb | |
| parent | 91be49b2d0635b3d666125790c59b057f956b2c0 (diff) | |
Inagua: Synchronize AMD/inagua mainboard.
AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
Persimmom update a lot in the last few month, sync these modification to inagua.
Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/542
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/amd/inagua/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/inagua/devicetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 32d9a2672c..62cf32d1f6 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -28,7 +28,7 @@ chip northbridge/amd/agesa/family14/root_complex # device pci 18.0 on # northbridge chip northbridge/amd/agesa/family14 # PCI side of HT root complex device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge + device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 device pci 1.1 on end # Internal Multimedia device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 @@ -65,14 +65,14 @@ chip northbridge/amd/agesa/family14/root_complex end end # kbc1100 end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 device pci 15.0 on end # PCIe PortA device pci 15.1 on end # PCIe PortB device pci 15.2 on end # PCIe PortC device pci 15.3 on end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 + device pci 16.0 on end # OHCI USB3 + device pci 16.2 on end # EHCI USB3 register "gpp_configuration" = "4" #1:1:1:1 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 |