AGESA boards: Relocate platform memory config

File buildOpts.c is a can of worms, pull platform memory
configuration in to OemCustomize.c. This array should be
assigned at runtime instead of linking a modified defaults
table.

Change-Id: I73d9d3fbc165e6c10472e105576d7c40820eaa6a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14528
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 0 insertions, 78 deletions

diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 57590a2e75..b4651b6bb3 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -310,81 +310,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
 
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-	//
-	// The following macros are supported (use comma to separate macros):
-	//
-	// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
-	//      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
-	//      AGESA will base on this value to disable unused MemClk to save power.
-	//      Example:
-	//      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
-	//           Bit AM3/S1g3 pin name
-	//           0   M[B,A]_CLK_H/L[0]
-	//           1   M[B,A]_CLK_H/L[1]
-	//           2   M[B,A]_CLK_H/L[2]
-	//           3   M[B,A]_CLK_H/L[3]
-	//           4   M[B,A]_CLK_H/L[4]
-	//           5   M[B,A]_CLK_H/L[5]
-	//           6   M[B,A]_CLK_H/L[6]
-	//           7   M[B,A]_CLK_H/L[7]
-	//      And platform has the following routing:
-	//           CS0   M[B,A]_CLK_H/L[4]
-	//           CS1   M[B,A]_CLK_H/L[2]
-	//           CS2   M[B,A]_CLK_H/L[3]
-	//           CS3   M[B,A]_CLK_H/L[5]
-	//      Then platform can specify the following macro:
-	//      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
-	//
-	// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
-	//      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
-	//      AGESA will base on this value to tristate unused CKE to save power.
-	//
-	// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
-	//      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
-	//      AGESA will base on this value to tristate unused ODT pins to save power.
-	//
-	// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
-	//      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
-	//      AGESA will base on this value to tristate unused Chip select to save power.
-	//
-	// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
-	//      Specifies the number of DIMM slots per channel.
-	//
-	// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
-	//      Specifies the number of Chip selects per channel.
-	//
-	// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
-	//      Specifies the number of channels per socket.
-	//
-	// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
-	//      Specifies DDR bus speed of channel ChannelID on socket SocketID.
-	//
-	// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
-	//      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
-	//
-	// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-	//      Byte6Seed, Byte7Seed, ByteEccSeed)
-	//      Specifies the write leveling seed for a channel of a socket.
-	//
-	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
-	PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"