mb/*/*: Remove AMD family14 boards

These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

7 files changed, 0 insertions, 1027 deletions

diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/inagua/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/inagua/acpi/ide.asl b/src/mainboard/amd/inagua/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/inagua/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl
deleted file mode 100644
index 8f8ea45e9e..0000000000
--- a/src/mainboard/amd/inagua/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/inagua/acpi/sata.asl b/src/mainboard/amd/inagua/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/inagua/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/inagua/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/inagua/acpi/superio.asl b/src/mainboard/amd/inagua/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/amd/inagua/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/inagua/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}