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authorFelix Held <felix-coreboot@felixheld.de>2022-10-12 23:46:53 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-10-14 00:00:48 +0000
commit61b50a64bf6eea248484c75568a2270004fc757d (patch)
tree0e540132fb82f6c38f5798ae3fd426e1a87fa634 /src/mainboard/amd/gardenia
parent4c1a389828dea21e4600440bcedcb41d74ac83dd (diff)
mb/amd/gardenia/devicetree: disable unused gpp_bridge_2
The board's PCIe port descriptors have the PCIe engine disabled, so update the devicetree accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic97a54c3cc762a36752d6b9f21467428912a9edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/68379 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/gardenia')
-rw-r--r--src/mainboard/amd/gardenia/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb
index 8e94c2e604..786003f753 100644
--- a/src/mainboard/amd/gardenia/devicetree.cb
+++ b/src/mainboard/amd/gardenia/devicetree.cb
@@ -14,7 +14,6 @@ chip soc/amd/stoneyridge
device ref gfx_hda on end
device ref gpp_bridge_0 on end # x4 PCIe slot
device ref gpp_bridge_1 on end # M.2 slot
- device ref gpp_bridge_2 on end # M.2 slot
device ref gpp_bridge_3 on end # x1 PCIe slot
device ref gpp_bridge_4 on end # Cardreader
device ref hda_bridge on end