diff options
| author | Marc Jones <marcj303@gmail.com> | 2017-05-05 16:15:31 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:46:30 +0000 |
| commit | 2df118cdf04c72156ca92b940063288968ca7cea (patch) | |
| tree | fe3ed54c1cc3fffc69ca07f52bfbafd2a67f5fe4 /src/mainboard/amd/gardenia/romstage.c | |
| parent | 1587dc8a2b4ddfe110cd0239c6506a320cccac96 (diff) | |
amd/gardenia: Switch to soc/amd/stoneyridge
Switch Garnenia mainboard to single soc/ directory structure.
Change-Id: I095804d603bcccf324d3244965081a9dccba62ae
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/gardenia/romstage.c')
| -rw-r--r-- | src/mainboard/amd/gardenia/romstage.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 75674a090a..678e1fbf83 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -22,7 +22,7 @@ #include <cpu/amd/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include <southbridge/amd/pi/hudson/hudson.h> +#include <soc/hudson.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -35,9 +35,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); -#if IS_ENABLED(CONFIG_HUDSON_UART) - configure_hudson_uart(); -#endif + if (IS_ENABLED(CONFIG_STONEYRIDGE_UART)) + configure_hudson_uart(); + post_code(0x31); console_init(); } |