diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-04-18 08:06:33 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-20 13:03:14 +0000 |
| commit | 6fcb9b00c8b7f820bb5ef81a83a24cd656654272 (patch) | |
| tree | 3cb9214d55eed3311fd071af4ca32739ba567df9 /src/mainboard/amd/gardenia/gpio.c | |
| parent | e6db1895617a50eabf9f1a0b40025e8a74817cc3 (diff) | |
soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure
The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.
BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.
Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/gardenia/gpio.c')
| -rw-r--r-- | src/mainboard/amd/gardenia/gpio.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 6672ea5c21..7c5f47b25a 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -24,7 +24,7 @@ * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ -const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { +static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* NFC PU */ PAD_GPO(GPIO_64, HIGH), /* PCIe presence detect */ @@ -45,7 +45,7 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), }; -const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { +static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* BT radio disable */ PAD_GPO(GPIO_14, HIGH), /* NFC wake */ @@ -56,13 +56,13 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { PAD_GPO(GPIO_70, HIGH), }; -const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size) +const struct soc_amd_gpio *early_gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_reset); return gpio_set_stage_reset; } -const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size) +const struct soc_amd_gpio *gpio_table(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage_ram); return gpio_set_stage_ram; |