diff options
| author | Marc Jones <marcj303@gmail.com> | 2016-09-20 20:36:08 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-16 23:01:44 +0100 |
| commit | 91135fef22262b1789abeb1a23efc43460cffa3d (patch) | |
| tree | 2f104054fa80f520be1fd22921f96c97bdc437dd /src/mainboard/amd/gardenia/devicetree.cb | |
| parent | 3a1fbeaf6608d56b1fce2dfb88c76821b05849db (diff) | |
mainboard/amd: Copy bettong to gardenia and update for build
Use bettong as the reference for the gardenia mainboard.
Update makefiles etc so it builds.
This patch intentionlly keeps the carrizo_fch.asl file to
remain synchronized with the AMD PI package.
Remove items that do not apply to the Stoney APU, rewrite the
comments associated with the PCIe devices, and fix up the
SPD register association to match the 00670F00 chip.h.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e)
Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17218
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/gardenia/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/gardenia/devicetree.cb | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb new file mode 100644 index 0000000000..946aae99e3 --- /dev/null +++ b/src/mainboard/amd/gardenia/devicetree.cb @@ -0,0 +1,69 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/pi/00670F00/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00670F00 + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00670F00 # CPU side of HT root complex + + chip northbridge/amd/pi/00670F00 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # M.2 slot + device pci 2.3 on end # M.2 slot + device pci 2.4 on end # x1 PCIe slot + device pci 2.5 on end # Cardreader + end #chip northbridge/amd/pi/00670F00 + + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.3 on end # LPC 0x790e + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1 + }" + + end #chip northbridge/amd/pi/00670F00 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00670F00/root_complex |