soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK

Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build.  The .S files
are mostly duplicated code from the old cache_as_ram.inc file.

The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.

Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S.  Drop the BIST check like other devices.

Move InitReset and InitEarly to bootblock.  These AGESA entry
points set some default settings, and release/recapture the
AP cores.  There are currently some early dependencies on
InitReset.  Future work should include:
 * Pull the necessary functionality from InitReset into bootblock
 * Move InitReset and InitEarly to car_stage_entry() and out of
   bootblock
   - Add a mechanism for the BSP to give the APs an address
     to call and skip most of bootblock and verstage (when
     available) (1)
   - Reunify BiosCallOuts.c and OemCustomize.c

(1) During the InitReset call, the BSP enables the APs by setting
    core enable bits in F18F0x1DC and APs begin fetching/executing
    from the reset vector.  The BSP waits for all APs to also
    reach InitReset, where they enter an endless loop.  The BSP
    sends a command to them to execute a HLT instruction and the
    BSP eventually returns from InitReset.  The goal would be to
    preserve this process but prevent APs from rerunning early
    code.

Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 0 insertions, 136 deletions

diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c
index 3a34761e50..3893e5dbcb 100644
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -18,142 +18,6 @@
 
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
-/* Port descriptor list for Gardenia Rev. B */
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x04, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x17, 0)
-	},
-	/* Disable M.2 x1 on lane 1, D2F3 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
-				2, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x17, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x13, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
-				2, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmL0sL1, 0x16, 0)
-	},
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DDI0 - eDP */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
-	},
-	/* DDI1 - DP */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	},
-	/* DDI2 - HDMI */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
-};
-
-static const UINT32 AzaliaCodecAlc286Table[] = {
-	0x00172051, 0x001721C7, 0x00172222, 0x00172310,
-	0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
-	0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
-	0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,
-	0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,
-	0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,
-	0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,
-	0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,
-	0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,
-	0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,
-	0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,
-	0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,
-	0x02050071, 0x02040014, 0x02050010, 0x02040C22,
-	0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,
-	0x0205002D, 0x02041020, 0x02050020, 0x02040000,
-	0x02050019, 0x02040817, 0x02050035, 0x02041AA5,
-	0x02050063, 0x02042906, 0x02050063, 0x02042906,
-	0xffffffff
-};
-
-CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
-	{ (UINT32) 0x10ec0286, AzaliaCodecAlc286Table},
-	{ (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF}
-};
-
-/*---------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the
- *    binary block interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------*/
-VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->PlatformConfig.AzaliaCodecVerbTable =
-					(UINT64)(UINTN)CodecTableList;
-}
-
 static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
 	DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
 	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),