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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-16 20:49:38 +0200
committerPatrick Georgi <pgeorgi@google.com>2016-09-20 19:06:28 +0200
commit6350a2e43f3657567f50160aa28d5d4305803be0 (patch)
tree66473657856456754ab78a636c393c1a744932be /src/mainboard/amd/dinar/gpio.c
parented5f159ed59c52a4731d07ef19bff8ef8de9ae14 (diff)
src/mainboard/a-trend - emulation: Add space around operators
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/amd/dinar/gpio.c')
-rw-r--r--src/mainboard/amd/dinar/gpio.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c
index 17097b33d1..affda6fd76 100644
--- a/src/mainboard/amd/dinar/gpio.c
+++ b/src/mainboard/amd/dinar/gpio.c
@@ -179,7 +179,7 @@ gpioEarlyInit(
RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO
RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
- // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
+ // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 0 (Output LOW)
RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
@@ -357,7 +357,7 @@ gpioEarlyInit(
}
// else
// { // 0 - AUTO
- // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
+ // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable)
// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
// }
@@ -377,7 +377,7 @@ gpioEarlyInit(
}
// else
// { // 0 - AUTO
- // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
+ // // set BIT3 = 1 (PULLUP disable), BIT4 = 0 (PULLDOWN Disable), BIT6 = 1 (output HIGH)
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
//