diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-03-10 21:31:56 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-11 14:26:12 +0000 |
commit | f4cfefe78895a445ec8d65176e67f5fcacdfac99 (patch) | |
tree | e996ed914f9d3a8a718618d9a73da11c46628734 /src/mainboard/amd/db-ft3b-lc/romstage.c | |
parent | e13bc1c12ce414307be780c30d2d22074a5fd2c5 (diff) |
mb/amd/db-ft3b-lc: Drop unmaintained ROMCC board
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.
Change-Id: Ib4a95c650cc4d1cddc2ba530c12ce448a1943b34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/amd/db-ft3b-lc/romstage.c')
-rw-r--r-- | src/mainboard/amd/db-ft3b-lc/romstage.c | 51 |
1 files changed, 0 insertions, 51 deletions
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c deleted file mode 100644 index 77250c2259..0000000000 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <amdblocks/acpimmio.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/pi/hudson/hudson.h> - -static void romstage_main_template(void) -{ - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - pm_io_write8(0xd2, 0); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - pm_io_write8(0xea, 1); -} |