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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-07-13 00:58:36 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-14 16:49:37 +0000 |
| commit | d1c33aeef4f8effbaacc54be99f9b7c5dd9fbcc5 (patch) | |
| tree | 8eb76945fa05c9ee9dec2fe8aad0ffc732510e77 /src/mainboard/amd/chausie | |
| parent | e479b3e356fae73b10deb147005c2e2a6be72d91 (diff) | |
mb/amd,google/*/port_descriptors: use dxio_link_hotplug_type enum values
Use the proper dxio_link_hotplug_type enum values for the link_hotplug
field in the DXIO descriptors to replace the magic values in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/chausie')
| -rw-r--r-- | src/mainboard/amd/chausie/port_descriptors.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c index 3105cf0c60..9a8c2740db 100644 --- a/src/mainboard/amd/chausie/port_descriptors.c +++ b/src/mainboard/amd/chausie/port_descriptors.c @@ -17,7 +17,7 @@ static const fsp_dxio_descriptor chausie_dxio_descriptors[] = { .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = 2, - .link_hotplug = 3, + .link_hotplug = HOTPLUG_ENHANCED, .clk_req = CLK_REQ3, }, { /* WIFI */ @@ -30,7 +30,7 @@ static const fsp_dxio_descriptor chausie_dxio_descriptors[] = { .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = 2, - .link_hotplug = 3, + .link_hotplug = HOTPLUG_ENHANCED, .clk_req = CLK_REQ1, }, { /* NVMe SSD */ @@ -43,7 +43,7 @@ static const fsp_dxio_descriptor chausie_dxio_descriptors[] = { .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = 2, - .link_hotplug = 3, + .link_hotplug = HOTPLUG_ENHANCED, .gpio_group_id = GPIO_27, .clk_req = CLK_REQ0, }, |