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authorSubrata Banik <subratabanik@google.com>2022-03-14 12:47:31 +0530
committerSubrata Banik <subratabanik@google.com>2022-03-19 05:27:28 +0000
commit7c477a9d1afe324050da6185ab3d22271c94fd7b (patch)
tree5b5a94b920f1d6d28a7672d965d83ea6d301c080 /src/mainboard/amd/chausie
parent9b6e851e5be25bd5b71b6d86a0502ec48a7d9fce (diff)
soc/intel/common/block/p2sb: Add helper function to enable BAR
This patch creates a new helper function to enable P2SB BAR. `p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F) and BAR address (combining high and low base addresses). BUG=b:224325352 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard/amd/chausie')
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