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authorFelix Held <felix-coreboot@felixheld.de>2022-02-13 23:26:44 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-30 01:17:53 +0000
commit2b4d1480d6afe04cc4065f27abf6fc0c1fa8d9ae (patch)
tree7050f26d1724b2b7fdc3e651f364f3908f1db29e /src/mainboard/amd/chausie
parentc55012bd2ad6646c91c443fe70347b79fa371390 (diff)
mb/amd/chausie/port_descriptors: update DXIO descriptors
Change the DXIO descriptors to match the default PCIe lane mapping on the chausie board. With this configuration and a board-level rework to bypass the EC control of the NVMe SSD power supply rail, this configuration results in the SSD being detected on the root port on bus 0 device 2 function 3 and usable as boot device. This was also validated against the schematics revision B. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/chausie')
-rw-r--r--src/mainboard/amd/chausie/port_descriptors.c87
1 files changed, 21 insertions, 66 deletions
diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c
index 46afa77599..02e82b8c97 100644
--- a/src/mainboard/amd/chausie/port_descriptors.c
+++ b/src/mainboard/amd/chausie/port_descriptors.c
@@ -5,91 +5,46 @@
#include <types.h>
static const fsp_dxio_descriptor chausie_czn_dxio_descriptors[] = {
- { /* MXM */
- .engine_type = PCIE_ENGINE,
- .port_present = true,
- .start_logical_lane = 16,
- .end_logical_lane = 23,
- .device_number = 1,
- .function_number = 1,
- .turn_off_unused_lanes = true,
- .clk_req = CLK_REQ0,
- .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
- },
- { /* SSD */
+ { /* GBE*/
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 0,
- .end_logical_lane = 1,
+ .end_logical_lane = 0,
.device_number = 2,
.function_number = 1,
+ .link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
- .clk_req = CLK_REQ5,
- .gpio_group_id = GPIO_40,
- .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+ .link_aspm = 2,
+ .link_hotplug = 3,
+ .clk_req = CLK_REQ3,
},
- { /* DT */
+ { /* WIFI */
.engine_type = PCIE_ENGINE,
.port_present = true,
- .start_logical_lane = 4,
- .end_logical_lane = 4,
+ .start_logical_lane = 1,
+ .end_logical_lane = 1,
.device_number = 2,
.function_number = 2,
+ .link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
- .clk_req = CLK_REQ4_GFX,
- .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
- },
- { /* WWAN */
- .engine_type = PCIE_ENGINE,
- .port_present = true,
- .start_logical_lane = 5,
- .end_logical_lane = 5,
- .device_number = 2,
- .function_number = 3,
- .turn_off_unused_lanes = true,
- .clk_req = CLK_REQ2,
- .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
- },
- { /* LAN */
- .engine_type = PCIE_ENGINE,
- .port_present = true,
- .start_logical_lane = 6,
- .end_logical_lane = 6,
- .device_number = 2,
- .function_number = 4,
- .turn_off_unused_lanes = true,
+ .link_aspm = 2,
+ .link_hotplug = 3,
.clk_req = CLK_REQ1,
- .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
- { /* WLAN */
+ { /* NVMe SSD */
.engine_type = PCIE_ENGINE,
.port_present = true,
- .start_logical_lane = 7,
- .end_logical_lane = 7,
- .device_number = 2,
- .function_number = 5,
- .turn_off_unused_lanes = true,
- .clk_req = CLK_REQ6,
- .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
- },
- { /* TB */
- .engine_type = PCIE_ENGINE,
- .port_present = true,
- .start_logical_lane = 8,
- .end_logical_lane = 11,
+ .start_logical_lane = 2,
+ .end_logical_lane = 3,
.device_number = 2,
- .function_number = 6,
+ .function_number = 3,
+ .link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
- .clk_req = CLK_REQ3,
- .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+ .link_aspm = 2,
+ .link_hotplug = 3,
+ .gpio_group_id = GPIO_27,
+ .clk_req = CLK_REQ0,
},
- { /* SATA */
- .engine_type = SATA_ENGINE,
- .port_present = true,
- .start_logical_lane = 2,
- .end_logical_lane = 3,
- .channel_type = SATA_CHANNEL_LONG,
- }
};
static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = {