mb/amd/chausie: add mainboard as copy of mb/amd/majolica

To have the new AMD Sabrina SoC code tested, add the AMD Chausie
mainboard as a copy of Majolica. This patch also changes the name from
Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC
and comments out the APCB_SOURCES since those aren't available in the
3rdparty/blobs repository yet.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/mainboard/amd/chausie/chromeos.c b/src/mainboard/amd/chausie/chromeos.c
new file mode 100644
index 0000000000..062fdad290
--- /dev/null
+++ b/src/mainboard/amd/chausie/chromeos.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	/* Chausie doesn't have a write protect pin */
+	return 0;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	/* No ChromeOS GPIOs */
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}