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| author | Tim Van Patten <timvp@google.com> | 2022-09-15 17:15:56 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-09-19 09:56:06 +0000 |
| commit | 1cf0acdc1ce54a8aa8b19378abf3075d23fa58ea (patch) | |
| tree | 2d40afee7c8bd64098a90cfefb68486b59028356 /src/mainboard/amd/chausie/chromeos.c | |
| parent | 11ca99550032b11aca8157d94fce728fec8981f2 (diff) | |
soc/amd/mendocino: Add low/no battery VRM limit registers
Add DPTC Low/No battery VRM limit registers to throttle the SOC.
BRANCH=none
BUG=b:217911928
TEST=Build skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/chausie/chromeos.c')
0 files changed, 0 insertions, 0 deletions