diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-02 16:40:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-18 16:23:27 +0000 |
| commit | 8c119079d1b9c11c1f9011ecf555a2fc6fd3cc34 (patch) | |
| tree | 8c5e9307beab5ae988834744e5e9a88dd5a62345 /src/mainboard/amd/birman | |
| parent | 8414eed5a04004a886cafc65763ff5448ff805dd (diff) | |
vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoC
Phoenix has one more Type C port and two more USB2 ports which are used
as the legacy USB part of the two USB4 ports. The USB struct version
numbers have also changed, since it's a newer and incompatible version
of that struct.
TEST=After changing FSP to not hard-code the USB PHY config, but use the
configuration provided by coreboot, and applying this patch, the USB
connector on the USB2 port 4 lines works.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If52934595dd612154b97e7b90dbd96243146017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/birman')
| -rw-r--r-- | src/mainboard/amd/birman/devicetree_phoenix.cb | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index 2fc78aa275..f1b88a37b5 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -127,6 +127,34 @@ chip soc/amd/phoenix .txhsxvtune = 0x3, .txrestune = 0x2, }, + .Usb2PhyPort[6] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[7] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, .Usb3PhyPort[0] = { .tx_term_ctrl = 0x2, .rx_term_ctrl = 0x2, @@ -147,6 +175,7 @@ chip soc/amd/phoenix }, .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C, .BatteryChargerEnable = 0, .PhyP3CpmP4Support = 0, }" |