diff options
| author | Martin Roth <gaumless@gmail.com> | 2023-01-09 21:38:09 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-22 00:39:02 +0000 |
| commit | 72f0501881194ed9b222470d82596264bb9c406a (patch) | |
| tree | 18e2203ad3f5fc0d1e1bdf95072b3830cfc3b6de /src/mainboard/amd/birman/chromeos.fmd | |
| parent | 0c45df8ddb9782a3d78ee507bacfc0a129be8b45 (diff) | |
mb/amd/(birman|mayan): Update chromeos.fmd files
Because the EFS is now fixed at 0xff020000, the ChromeOS RO region needs
to be moved to the bottom of the ROM area to cover that space.
The RO Region 6MiB, but you can't actually set 6MiB as RO - it's either
4 or 8MiB, so that's adjusted. To leave some room for the RW_LEGACY
region, the two RW regions are adjusted to 3MiB each, which should be
plenty.
The GBB region had to be moved from the front of the WP_RO region to the
end to avoid conflicting with the EFS, which needs to be inside the
coreboot cbfs area.
Also get rid of AMD_FWM_POSITION_INDEX. The FWM position is no longer
needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I683155ec0f4e6a62d862b9e2fa76af45f4cd5493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/amd/birman/chromeos.fmd')
| -rw-r--r-- | src/mainboard/amd/birman/chromeos.fmd | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/amd/birman/chromeos.fmd b/src/mainboard/amd/birman/chromeos.fmd index c28070ad11..538dfbd1c6 100644 --- a/src/mainboard/amd/birman/chromeos.fmd +++ b/src/mainboard/amd/birman/chromeos.fmd @@ -1,13 +1,21 @@ FLASH@0xFF000000 16M { SI_BIOS { - EC 4K - RW_MRC_CACHE(PRESERVE) 120K - RW_SECTION_A 4M { + WP_RO 8M { + EC 4K + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + COREBOOT(CBFS) + GBB 448K + } + } + RW_SECTION_A 3M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 256 } - RW_SECTION_B 4M { + RW_SECTION_B 3M { VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 256 @@ -21,14 +29,6 @@ FLASH@0xFF000000 16M { RW_NVRAM(PRESERVE) 20K SMMSTORE(PRESERVE) 64K RW_LEGACY(CBFS) - WP_RO@10M 6M { - RO_VPD(PRESERVE) 16K - RO_SECTION { - FMAP 2K - RO_FRID 64 - GBB@4K 448K - COREBOOT(CBFS) - } - } + RW_MRC_CACHE(PRESERVE) 120K } } |