src: Get rid of unneeded whitespace

Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

3 files changed, 22 insertions, 22 deletions

diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb
index 0bcc9c16af..ba6a0fafcf 100644
--- a/src/mainboard/amd/bimini_fam10/devicetree.cb
+++ b/src/mainboard/amd/bimini_fam10/devicetree.cb
@@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
-					device pci 0.0 on end # HT  	0x9600
+					device pci 0.0 on end # HT	0x9600
 					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
 					device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
 					device pci 3.0 off end # PCIE P2P bridge	0x960b
@@ -38,7 +38,7 @@ chip northbridge/amd/amdfam10/root_complex
 					device pci 12.2 on end # USB
 					device pci 13.0 on end # USB
 					device pci 13.2 on end # USB
-	 				device pci 14.0 on # SM
+					device pci 14.0 on # SM
 						chip drivers/generic/generic #dimm 0-0-0
 							device i2c 50 on end
 						end
diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl
index b6a8e17a42..96dc819045 100644
--- a/src/mainboard/amd/bimini_fam10/dsdt.asl
+++ b/src/mainboard/amd/bimini_fam10/dsdt.asl
@@ -234,9 +234,9 @@ DefinitionBlock (
 		PWMK, 1,
 		PWNS, 1,
 
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
+		/*	Offset(0x61), */	/*  Options_1 */
+		/*		,7,  */
+		/*		R617,1, */
 
 		Offset(0x65),	/* UsbPMControl */
 		, 4,
@@ -832,7 +832,7 @@ DefinitionBlock (
 
 		/* On older chips, clear PciExpWakeDisEn */
 		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
+		*	Store(0,\_SB.PWDE)
 		*}
 		*/
 
@@ -847,13 +847,13 @@ DefinitionBlock (
 	*  used, so it could be removed.
 	*
 	*
-	*  	\_GTS OEM Going To Sleep method
+	*	\_GTS OEM Going To Sleep method
 	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
 	*
-	*  	Exit:
-	*  		-none-
+	*	Exit:
+	*		-none-
 	*
 	*  Method(\_GTS, 1) {
 	*  DBGO("\\_GTS\n")
@@ -1020,7 +1020,7 @@ DefinitionBlock (
 
 		/*  PCIe HotPlug event  */
 		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
+		*	DBGO("\\_GPE\\_L0F\n")
 		* }
 		*/
 
@@ -1043,19 +1043,19 @@ DefinitionBlock (
 
 		/*  GPM0 SCI event - Moved to USB.asl */
 		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
+		*	DBGO("\\_GPE\\_L13\n")
 		* }
 		*/
 
 		/*  GPM1 SCI event - Moved to USB.asl */
 		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
+		*	DBGO("\\_GPE\\_L14\n")
 		* }
 		*/
 
 		/*  GPM2 SCI event - Moved to USB.asl */
 		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
+		*	DBGO("\\_GPE\\_L15\n")
 		* }
 		*/
 
@@ -1067,7 +1067,7 @@ DefinitionBlock (
 
 		/*  GPM8 SCI event - Moved to USB.asl */
 		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
+		*	DBGO("\\_GPE\\_L17\n")
 		* }
 		*/
 
@@ -1084,7 +1084,7 @@ DefinitionBlock (
 
 		/*  GPM4 SCI event - Moved to USB.asl */
 		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
+		*	DBGO("\\_GPE\\_L19\n")
 		* }
 		*/
 
@@ -1115,7 +1115,7 @@ DefinitionBlock (
 
 		/*  GPIO2 or GPIO66 SCI event  */
 		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
+		*	DBGO("\\_GPE\\_L1E\n")
 		* }
 		*/
 
@@ -1125,7 +1125,7 @@ DefinitionBlock (
 		* }
 		*/
 
-	} 	/* End Scope GPE */
+	}	/* End Scope GPE */
 
 	#include "acpi/usb.asl"
 
@@ -1477,7 +1477,7 @@ DefinitionBlock (
 				)
 #if 0
 				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
@@ -1607,7 +1607,7 @@ DefinitionBlock (
 
 				/* On older chips, clear PciExpWakeDisEn */
 				/*if (LLessEqual(\SBRI, 0x13)) {
-				*    	Store(0,\PWDE)
+				*	Store(0,\PWDE)
 				* }
 				*/
 			} /* End Method(_SB._INI) */
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 0c26416e75..d4397b2372 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -80,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		/* enable port80 decoding and southbridge poweron init */
 		sb800_lpc_port80();
-		inb(0x80); 	/* Wait sometime before post to port80, otherwise reset was needed. */
+		inb(0x80);	/* Wait sometime before post to port80, otherwise reset was needed. */
 	}
 
 	post_code(0x30);