diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2011-01-01 18:40:02 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2011-01-01 18:40:02 +0000 |
commit | 26c182340fa5569f034a50010bb6d47ed13e5fd6 (patch) | |
tree | 93b42e7b97b8ccf1728a7303e9c34eee93507629 /src/mainboard/amd/bimini_fam10/romstage.c | |
parent | f7e7519ff56a05b2f89eb647a7764afda032aeca (diff) |
AMD Bimini: Small fixes, and updates to recent trunk conventions.
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed
to HAVE_DEBUG_CAR in r5898.
- Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.
- Drop obsolete/unused COMPRESS, see r6145.
- Drop obsolete SET_NB_CFG_54, see r6086.
- Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077.
Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.
- Rename some GENERATE_* options to HAVE_*, see r6027.
- Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.
- Drop ACPI_SSDTX_NUM, the global default is 0 already.
- Random whitespace and coding style fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/bimini_fam10/romstage.c')
-rw-r--r-- | src/mainboard/amd/bimini_fam10/romstage.c | 34 |
1 files changed, 5 insertions, 29 deletions
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 29b1be3afe..3709862e5f 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -21,21 +21,10 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 - -#define SET_NB_CFG_54 1 - -//used by raminit -#define QRANK_DIMM_SUPPORT 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -48,47 +37,36 @@ #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" - #include <console/loglevel.h> #include "cpu/x86/bist.h" - #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" - #include "southbridge/amd/rs780/early_setup.c" #include <SbEarly.h> #include <SBPLATFORM.h> /* SB OEM constants */ #include <sb800_smbus.h> #include "northbridge/amd/amdfam10/debug.c" - static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) { - int result; - result = do_smbus_read_byte(SMBUS_IO_BASE, device, address); - return result; + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" - #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" - #include "northbridge/amd/amdfam10/early_ht.c" #define RC00 0 @@ -110,11 +88,9 @@ void soft_reset(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { @@ -183,20 +159,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); - #endif +#endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); - #if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |