diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2011-01-01 18:40:02 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2011-01-01 18:40:02 +0000 |
| commit | 26c182340fa5569f034a50010bb6d47ed13e5fd6 (patch) | |
| tree | 93b42e7b97b8ccf1728a7303e9c34eee93507629 /src/mainboard/amd/bimini_fam10/reset.c | |
| parent | f7e7519ff56a05b2f89eb647a7764afda032aeca (diff) | |
AMD Bimini: Small fixes, and updates to recent trunk conventions.
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed
to HAVE_DEBUG_CAR in r5898.
- Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.
- Drop obsolete/unused COMPRESS, see r6145.
- Drop obsolete SET_NB_CFG_54, see r6086.
- Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077.
Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.
- Rename some GENERATE_* options to HAVE_*, see r6027.
- Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.
- Drop ACPI_SSDTX_NUM, the global default is 0 already.
- Random whitespace and coding style fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/bimini_fam10/reset.c')
| -rw-r--r-- | src/mainboard/amd/bimini_fam10/reset.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/mainboard/amd/bimini_fam10/reset.c b/src/mainboard/amd/bimini_fam10/reset.c index f76db04bc6..0b32bedb36 100644 --- a/src/mainboard/amd/bimini_fam10/reset.c +++ b/src/mainboard/amd/bimini_fam10/reset.c @@ -17,10 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <reset.h> -#include <arch/io.h> /*inb, outb*/ -#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ +#include <arch/io.h> +#include <arch/romcc_io.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) @@ -33,13 +32,12 @@ static inline void set_bios_reset(void) { - u32 nodes; - u32 htic; + u32 nodes, htic; device_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; @@ -63,4 +61,3 @@ void soft_reset(void) /* link reset */ outb(0x06, 0x0cf9); } - |