remove the code which is not ready to release.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 0 insertions, 160 deletions

diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
deleted file mode 100644
index c14e769b41..0000000000
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include "pmio.h"
-#include <cpu/amd/amdfam10_sysconf.h>
-
-extern int bus_isa;
-extern u8 bus_rs780[11];
-extern u8 bus_sb800[2];
-extern u32 apicid_sb800;
-extern u32 bus_type[256];
-extern u32 sbdn_rs780;
-extern u32 sbdn_sb800;
-
-u8 intr_data[] = {
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-	[0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x10,0x11,0x12,0x13
-};
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	u32 dword;
-	u8 byte;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LAPIC_ADDR);
-
-	smp_write_processors(mc);
-
-	get_bus_conf();
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* I/O APICs:   APIC ID Version State   Address */
-
-	dword = 0;
-	dword = pm_ioread(0x34) & 0xF0;
-	dword |= (pm_ioread(0x35) & 0xFF) << 8;
-	dword |= (pm_ioread(0x36) & 0xFF) << 16;
-	dword |= (pm_ioread(0x37) & 0xFF) << 24;
-	smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
-
-	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-		outb(byte | 0x80, 0xC00);
-		outb(intr_data[byte], 0xC01);
-	}
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
-#define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
-#else
-#define PCI_INT(bus, dev, fn, pin)
-#endif
-
-	PCI_INT(0x0, 0x14, 0x0, 0x10);
-	/* HD Audio: */
-	PCI_INT(0x0, 0x14, 0x2, 0x12);
-
-	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-
-	/* sata */
-	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
-
-	/* on board NIC & Slot PCIE.  */
-	/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
-/* 	PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
-	PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
-	/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
-	PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
-	/* configuration B doesnt need dev 5,6,7 */
-	/*
-	 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
-	 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
-	 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
-	 */
-	PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
-	PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
-
-	/* PCI slots */
-	/* PCI_SLOT 0. */
-	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-	/* PCI_SLOT 1. */
-	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-	/* PCI_SLOT 2. */
-	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	mc->mpe_checksum =
-	    smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
-		     mc, smp_next_mpe_entry(mc));
-	return smp_next_mpe_entry(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr);
-	return (unsigned long)smp_write_config_table(v);
-}