mainboard/amd/bilby: Add Bilby CRB board

Bilby is the reference board for AMD Raven, Raven2 and Picasso APUs.
Bilby mainboard code is taken from mandolin variant Cereme.
These new files are a renamed copy and subsequent patches will be
applied to create a working bilby implementation.

Change-Id: I426966d782e259a971ec36bac2498bc62b4ce7e2
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 33 insertions, 0 deletions

diff --git a/src/mainboard/amd/bilby/gpio.c b/src/mainboard/amd/bilby/gpio.c
new file mode 100644
index 0000000000..999672e47e
--- /dev/null
+++ b/src/mainboard/amd/bilby/gpio.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "gpio.h"
+
+/*
+ * As a rule of thumb, GPIO pins used by coreboot should be initialized at
+ * bootblock while GPIO pins used only by the OS should be initialized at
+ * ramstage.
+ */
+static const struct soc_amd_gpio gpio_set_stage_ram[] = {
+	/* EC SCI# */
+	PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW),
+	/* I2S SDIN */
+	PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
+	/* I2S LRCLK */
+	PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
+	/* not Blink */
+	PAD_GPI(GPIO_11, PULL_UP),
+	/* APU_ALS_INT# */
+	PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
+	/* SD card detect */
+	PAD_GPI(GPIO_31, PULL_UP),
+	/* NFC IRQ */
+	PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
+	/* NFC wake output# */
+	PAD_GPO(GPIO_89, HIGH),
+};
+
+void mainboard_program_gpios(void)
+{
+	program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
+}