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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-02-28 17:20:05 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-02 23:43:12 +0000 |
| commit | 528ae9e811939c5e453c57aea79bc420a5f5fc43 (patch) | |
| tree | bf8437ddd8d8852dc3b26b0ddcab584f9ba58d41 /src/mainboard/amd/bettong | |
| parent | 23f870ad3a59983533c502e5dd744edde054d193 (diff) | |
soc/tigerlake: Correct FSP log interface
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART.
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART
BUG=None
BRANCH=None
TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/bettong')
0 files changed, 0 insertions, 0 deletions