diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-03-10 21:33:57 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-11 14:26:35 +0000 |
| commit | 3002eb42ed5e844ac6e3967ca0f66e3ae1a9e74d (patch) | |
| tree | 1b5124e8bf39ecec1ed2fa28d816c5f18d6d52f9 /src/mainboard/amd/bettong/dsdt.asl | |
| parent | f4cfefe78895a445ec8d65176e67f5fcacdfac99 (diff) | |
mb/amd/bettong: Drop unmaintained ROMCC board
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.
Change-Id: I1bce09ba5041a6636f900de611846467653f35a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/amd/bettong/dsdt.asl')
| -rw-r--r-- | src/mainboard/amd/bettong/dsdt.asl | 84 |
1 files changed, 0 insertions, 84 deletions
diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl deleted file mode 100644 index f6449ece99..0000000000 --- a/src/mainboard/amd/bettong/dsdt.asl +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* DefinitionBlock Statement */ -#include <arch/acpi.h> -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - OEM_ID, - ACPI_TABLE_CREATOR, - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ - - /* Globals for the platform */ - #include "acpi/mainboard.asl" - - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - - /* PCI IRQ mapping for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/pcie.asl> - - /* Describe the processor tree (\_PR) */ - #include <cpu/amd/pi/00660F01/acpi/cpu.asl> - - /* Contains the supported sleep states for this chipset */ - #include <southbridge/amd/common/acpi/sleepstates.asl> - - /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ - #include "acpi/sleep.asl" - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ - #include "acpi/routing.asl" - - Device(PWRB) { - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) - Name(_STA, 0x0B) - } - - Device(PCI0) { - /* Describe the AMD Northbridge */ - #include <northbridge/amd/pi/00660F01/acpi/northbridge.asl> - - /* Describe the AMD Fusion Controller Hub Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/fch.asl> - } - - /* Describe PCI INT[A-H] for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> - - /* Describe the devices in the Southbridge */ - #include "acpi/carrizo_fch.asl" - - } /* End \_SB scope */ - - /* Describe SMBUS for the Southbridge */ - #include <southbridge/amd/pi/hudson/acpi/smbus.asl> - - /* Define the General Purpose Events for the platform */ - #include "acpi/gpe.asl" -} -/* End of ASL file */ |