diff options
author | Gabe Black <gabeblack@google.com> | 2013-06-06 00:14:08 -0700 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 21:46:12 +0200 |
commit | 1162103958fad815e10b90524560b3b81f2c0b18 (patch) | |
tree | bec7aad12464c8ed8ee196d4a5d616358bc65ad1 /src/mainboard/advantech | |
parent | d63bddc4991d9ace037fd716b29c3f7253e9ac94 (diff) |
exynos5420: Fix some problems with the clock management code.
The code which figured out the rate of the input clock to a peripheral was
doing several things wrong. First, it was using the wrong values when
determing what the source of a clock was set to. Second, it was using the
wrong offset into that register to find the current source setting.
This change fixes the constants which select a clock source which get some
more things working, but doesn't attempt to fix the bit position table.
Change-Id: Id7482ee1c78cec274353bae3ce2dccb84705c66a
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3665
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/advantech')
0 files changed, 0 insertions, 0 deletions