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authorDuncan Laurie <dlaurie@chromium.org>2012-06-23 15:22:43 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-24 23:49:28 +0200
commit51cb26d92a2ddac8d71fe0e5970ed208110add71 (patch)
treed64e41f2ff26f489a17f8f11d4ca3a23680b0658 /src/mainboard/advansus/a785e-i/reset.c
parent181bbdd51cb4ec318e8b44c1ca652310bf6abb22 (diff)
SMM: Fix state save map for sandybridge and TSEG
There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1309 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/advansus/a785e-i/reset.c')
0 files changed, 0 insertions, 0 deletions