diff options
author | Kerry She <kerry.she@amd.com> | 2011-05-07 09:15:02 +0000 |
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committer | Kerry She <Kerry.She@amd.com> | 2011-05-07 09:15:02 +0000 |
commit | 6401fdb02593940e3091b1d200c64d9c1d7269f3 (patch) | |
tree | df835364607d2fcfa68d6fd2e5d1472d7d307c72 /src/mainboard/advansus/a785e-i/Makefile.inc | |
parent | faafd14fe0d18de1f71491f4503f36a4f9d9a188 (diff) |
ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 platform.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/advansus/a785e-i/Makefile.inc')
-rw-r--r-- | src/mainboard/advansus/a785e-i/Makefile.inc | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc new file mode 100644 index 0000000000..94433b7f3a --- /dev/null +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -0,0 +1,19 @@ +#romstage-y += reset.c #FIXME romstage have include test_rest.c +romstage-y += pmio.c + +ramstage-y += reset.c +ramstage-y += pmio.c + +#SB800 CIMx share AGESA V5 lib code +ifneq ($(CONFIG_AMD_AGESA),y) + romstage-y += ../../../vendorcode/amd/agesa/Lib/amdlib.c + ramstage-y += ../../../vendorcode/amd/agesa/Lib/amdlib.c + + AGESA_INC := -Isrc/vendorcode/amd/agesa/ \ + -Isrc/vendorcode/amd/agesa/Include \ + -Isrc/vendorcode/amd/agesa/Proc/IDS/ \ + -Isrc/vendorcode/amd/agesa/Proc/CPU/ \ + -Isrc/vendorcode/amd/agesa/Proc/CPU/Family + + CFLAGS += $(AGESA_INC) +endif |