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authorSubrata Banik <subrata.banik@intel.com>2018-01-18 15:20:21 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-01-24 13:26:40 +0000
commita971254d6756b1bcb78d9ac7a98789e995792a7a (patch)
treef42530a3b03d03dc6856b09321b418d7a4b04be5 /src/mainboard/adlink
parentd99f9d526f9e46442b1d0158d7f881202b293183 (diff)
soc/intel/cannonlake: Port SD Controller W/A from Intel Reference code
Solution: To do an additional config read to the SD controller after the controller has been power gated (put to D3) Change-Id: Ia2438c767332b0e2d413c71b06b052bf9ab4a96c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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