adi/rc-dff: Add Initial implementaion

* Add ADI vendor

Copy Intel Mohon Peak mainboard to ADI vendor. No functional changes,
only string and ifdef names changed.

Change-Id: I25a6d0ec549c79a8ff149d39f72648f625dc36fe
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/14778
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 82 insertions, 0 deletions

diff --git a/src/mainboard/adi/rcc-dff/Kconfig b/src/mainboard/adi/rcc-dff/Kconfig
new file mode 100644
index 0000000000..82df6bc74c
--- /dev/null
+++ b/src/mainboard/adi/rcc-dff/Kconfig
@@ -0,0 +1,82 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+if BOARD_ADI_RCC_DFF
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CPU_INTEL_SOCKET_RPGA989
+	select NORTHBRIDGE_INTEL_FSP_RANGELEY
+	select SOUTHBRIDGE_INTEL_FSP_RANGELEY
+	select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select MMCONF_SUPPORT
+	select POST_IO
+	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
+
+config MAINBOARD_DIR
+	string
+	default adi/rcc-dff
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ADI RCC-DFF"
+
+config MAX_CPUS
+	int
+	default 16
+
+config CACHE_ROM_SIZE_OVERRIDE
+	hex
+	default 0x800000
+
+config FSP_FILE
+	string
+	default "../intel/fsp/rangeley/FvFsp.bin"
+
+config CBFS_SIZE
+	hex
+	default 0x00200000
+
+config ENABLE_FSP_FAST_BOOT
+	bool
+	depends on HAVE_FSP_BIN
+	default y
+
+config VIRTUAL_ROM_SIZE
+	hex
+	depends on ENABLE_FSP_FAST_BOOT
+	default 0x400000
+
+config FSP_PACKAGE_DEFAULT
+	bool "Configure defaults for the Intel FSP package"
+	default n
+
+config UART_FOR_CONSOLE
+	int
+	default 1
+	help
+	  The Mohon Peak board uses COM2 (2f8) for the serial console.
+
+config PAYLOAD_CONFIGFILE
+	string
+	default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
+	help
+	  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
+	  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
+	  we put the SeaBIOS buffer area down in the 0x9000 segment.
+
+endif # BOARD_ADI_RCC_DFF